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I'm new with vhdl code. I have three (and) components and one (voter) component. I don't want to active those (and) components in one time, I want to active the first then, when I have the answer of the first (and) component, active the second and when I have the answer of the second, active the third. Then vote between three answers. what should I do? Please help me with this problem.

here is the top entity:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity triple is
port ( A, B: in std_logic;
      O: out std_logic);
end triple;   
architecture Behavioral of triple is
component and_1 is
port (a1, b1: in std_logic;
      o1 : out std_logic);
end component;

component and_2 is
port (a2, b2: in std_logic;
      o2 : out std_logic);
end component;

component and_3 is
port (a3, b3: in std_logic;
      o3 : out std_logic);
end component;

component voter is 
port (a, b, c: in std_logic;
      output : out std_logic);
end component;
signal out1, out2, out3 : std_logic;
begin
 -- ands---
 firstand: and_1 port map (A, B, out1);
 secondand: and_2 port map (A, B, out2);
 thirdand: and_3 port map (A, B, out3);
 ---Voter---
 vote: voter port map (out1, out2, out3, O);
end Behavioral;

The first and component:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_1 is
port (a1, b1: in std_logic;
      o1 : out std_logic);
end and_1;

architecture Behavioral of and_1 is

begin
o1 <= a1 and b1;

end Behavioral;

The second and the third components are like the first.

Here is the voter component:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity voter is
port (a, b, c: in std_logic;
      output : out std_logic);
end voter;

architecture Behavioral of voter is
begin
output <= (a and b) or ( b and c) or (a and c);
end Behavioral;
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  • 1
    \$\begingroup\$ Are you strictly doing this for simulation purposes, or do you want to synthesize this in actual logic at some point? \$\endgroup\$
    – crj11
    Commented Sep 15, 2018 at 14:30
  • \$\begingroup\$ Yes dear, I have one tool and I want to measure the amount of power when one component works and the others don't work ( They have just leakage power when they don't work ). But I don't know how respectively active them. \$\endgroup\$
    – Masoum
    Commented Sep 15, 2018 at 15:51

1 Answer 1

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VHDL is a hardware description language...you don't activate components, you instantiate them. All of your components, the three ands and the voter, will be created and will exist forever (i.e. as long as the simulation is running or until you reprogram the FPGA). You need to change your perspective on "programming" with an HDL.

Having said that, a combinational component is essentially idle until its inputs change. You don't explicitly activate it, it just works concurrently and asynchronously along with all of the other combinational components.

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  • \$\begingroup\$ Yes, but I mean I want to gate two components one time and have just one answer and register the answer. Then I want to do it for the others. Then vote between three answers. \$\endgroup\$
    – Masoum
    Commented Sep 15, 2018 at 15:57
  • \$\begingroup\$ When you start talking about "register the answer" and "then" you are getting into synchronous sequential systems. You will need to learn about flip-flops, registers, and pipelines. You might even be in finite state machine (FSM) territory. \$\endgroup\$ Commented Sep 15, 2018 at 16:20
  • \$\begingroup\$ Your question needs rethinking. Look at 'resource sharing' concept. It is a sequential perspective not combinational. You can do it with 1 instead of 3 components by waiving latency. but it does not apply to the AND gate. Used for valuable components such as multiplier. \$\endgroup\$ Commented Mar 7, 2021 at 10:59
  • \$\begingroup\$ You make a circuit like using 74 series ICs are connected to each other with cables on a breadboard. \$\endgroup\$ Commented Mar 7, 2021 at 11:05

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