I'm really trying to understand my voltage regulator (LM350T), but I think I'm still missing a few things. If I add cap C3 (I've tried 0.1uF and 10uF) to the output in the circuit below (note that the regulator should be LM350T), I get a rapid voltage rise (e.g. from 11V to 16.36V, or 6.4V to 9.8V), then a verrrry slow drop after that.

This shouldn't be right: the cap is not "part of" the regulator circuit in that it doesn't pass information between the adjust and out pins as far as I can see. The effect I describe should be in the capacitor itself across the plates, not in the regulator output. So I don't think it should have any effect. But it does.

Beyond that, it increases my minimum voltage out from ~1.25V to nearly 1.5V, and this doesn't appear to be discussed in the datasheet. I mean, I guess they don't have to include in the applications that the addition of an output cap will significantly change the minimum circuit voltage, but it seems like the TI sheet would have at least mentioned it, as it is very complete otherwise.


simulate this circuit – Schematic created using CircuitLab

  • \$\begingroup\$ Why C2 ? THat hurts your load regulation by suppressing step load feedback by integration.. What test current or load R pulse or otherwise is used and results. IS there thermal limiting shutdown? \$\endgroup\$ Commented Sep 17, 2018 at 15:18
  • \$\begingroup\$ C2 is recommended by the datasheet to limit ripple. Right now I am just seeing this happen with my multimeter/scope. I have no function generators or anything to give a more complete test. I have put 10kR across the output as a sample load, but no change. \$\endgroup\$ Commented Sep 17, 2018 at 15:21
  • \$\begingroup\$ it would probably drop to Vmin with 1k load or 100Ohm and fix the overshoot issue, but use my answer \$\endgroup\$ Commented Sep 17, 2018 at 16:11
  • \$\begingroup\$ C3 is part of the circuit --- it produces a pole (and probably a zero due to parasitics) in the loop gain of the regulator circuit. Many regulators (I don't know about LM350) can be unstable if the output capacitor has too low an ESR. (Did you use an electrolytic as indicated in the datasheet, or did you use a ceramic capacitor at C3?) \$\endgroup\$
    – The Photon
    Commented Sep 17, 2018 at 16:42
  • \$\begingroup\$ @ThePhoton This is old school BJT LDO so low ESR has no instability issues. Move C2 in parallel with C3. Vmin is due to ignoring Min load current. My fix will improve transient response which is not reported as problem but C2 on ADJ with no load will raise Vout min. \$\endgroup\$ Commented Sep 17, 2018 at 16:54

1 Answer 1


The purpose of your C2 is to create a slower turn-on and even slower droop as a result of overshoot since there is no pull down driver, just pullup. (Darlington NPN)

A secondary misleading advantage is to reduce massive full wave rectified in input ripple to output by some minor amount. The disadvantage is it seems to raise your Vmin adjustment range. This the point when R1 is near max but maybe not exactly 0 Ohms and the output rises for you. (corrected)

My suggestion is to move C2 to output
You do not report an input or output ripple issue. Then move diode to in-output to protect against input short circuit damaging output. (opt.)

Also, make sure you have adequate heatsink+fan if you plan to use 3A at 10V with an 8V drop or 24 Watt dissipation.

enter image description here

SPEC says MINIMUM LOAD CURRENT = 10mA max ( not 10V over 10k=1mA)

Low ESR is not a problem for C3 as this is a bipolar LDO not a MOSFET LDO which can suffer from low loop gain from excessive low ESR.

  • \$\begingroup\$ Yes, I see that it is much more sluggish with the ADJ cap, thanks for that. Also, the minimum load current you have here is for the LM150, the LM350 has minimum load current of 10mA max. \$\endgroup\$ Commented Sep 17, 2018 at 19:33
  • \$\begingroup\$ ok , you're welcome. They have CC chips for 10mA that can drive an LED or you can put on a dummy load or roll your own 2 transistor CC sink with LED using 230mW max on transistor at 25V \$\endgroup\$ Commented Sep 17, 2018 at 19:51
  • \$\begingroup\$ or just rely on your application to draw this. if you are using 1.25V \$\endgroup\$ Commented Sep 17, 2018 at 19:57
  • \$\begingroup\$ You're missing the point. C2 would slow down loop response if the IC feedback input were across the 5k pot. But input is obviously across VREF/OUT so voltage divider shall be seen upside down and C2 will actually speed up loop as a leed/lag compensator. \$\endgroup\$
    – carloc
    Commented Sep 18, 2018 at 0:10
  • \$\begingroup\$ @carloc ref. his schematic. Vout= 1.25(1+R1/R2) and C2//R1 so as power is applied R1=0 at t=0 with minimum output rising slowly due to C2. PlsAdvise REFDES are reversed from datasheet. \$\endgroup\$ Commented Sep 18, 2018 at 1:14

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