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I have a register of around 120bits, where data is shifted in lsb first, at some point I want to assign it to smaller registers but instead of truncating the most significant bits, I'd like to truncate the least significant bits. In essence I want to keep the n most significant bits of a register.

The current way I'm doing it is for each register assign from MSB index of big register for a width of register width like:

rSmall1 <= rBig[BIG_REG_MSB_INDEX -: RSMALL1_WIDTH];
rSmall2 <= rBig[BIG_REG_MSB_INDEX -: RSMALL2_WIDTH];
[...]
rSmalln <= rBig[BIG_REG_MSB_INDEX -: RSMALLn_WIDTH];

While it works it clutters up pretty fast so, Is there a simpler way to do this same operation for any width of rSmalln?

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There is no easier way to do this in Verilog. A logical shift right requires similar width parameters.

This would be easier using SystemVerilog's streaming operator which left justifies assignments.

bit [BIG_REG_MSB_INDEX:0] filler;

{{>>{rSmall1,Filler}} <= rBig;
{{>>{rSmall2,Filler}} <= rBig;
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  • \$\begingroup\$ Guess I'll have to stick with what I have. System verilog not allowed per company rules. \$\endgroup\$ – NeonMan Sep 17 '18 at 16:13

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