Pulse Train Sampling Rate

Question

Assume I have a pulse train with frequency of F Hertz. A normal square wave has all odd harmonics. From Nyquist, if I want to "Reconstruct" the waveform, sampling frequency Fs should be at least 2*(2k+1)*F for some large k.

What if I don't want to reconstuct the waveform and just want to able to detect Highs and Lows? UART receivers for example, sample at 8 or 16 times the frequency F. Is that because they just want to detect High and Lows? They don't want to actually reconstruct the waveform, are just interested in certain points.

Answer 1

You need to describe your "pulse train" in greater detail, but in general, your sample interval (period) needs to be strictly shorter than the shortest "high" or shortest "low" that can appear in your signal. Otherwise, you risk missing a high or a low altogether.

UARTs use high sample rates in order to deal with "sloppy" signals that might have significant noise or distortion. It also makes them more tolerant of speed errors between the two ends of the connection.

Answer 2

The A in UART = asynchronous. This refers to the free running 16x clock generated by the receiver to look for the leading start bit edge then choose the middle of the bit using a 1x inverted clock( = bit rate) now synced to that edge. Since there is a small frequency difference, the clock phase slowly drifts early or late but no more than typically than 100ppm*10bits=0.1%.

This is done for each word with start and stop bit as a word frame check. This accommodates some bit shift due to signal distortion and clock frequency difference between the sender and receiver which are generally well within 100ppm.

Since it is already binary logic determined by the Rx threshold, which is the same as TTL @1.3V, while the signal is +/-V, there is no need to sample any more than this 16x f, nor any savings in silicon to sample less than this. So a UART 16x Clock has become a de facto standard. The exception is the highest bit rates, where an only 8x clock is available in some cases with a slight loss in the clock to data edge margin for error due to all the effects of bit phase shift.

If you were wanting to have synchronous data without start and stop bits then a PLL SERDES clock sync would be used which normally uses a clock at the same rate as the symbol rate. This is followed by a search for a unique frame sync pattern then it can decode the stream.

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