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Assume I have a pulse train with frequency of F Hertz. A normal square wave has all odd harmonics. From Nyquist, if I want to "Reconstruct" the waveform, sampling frequency Fs should be at least 2*(2k+1)*F for some large k.

What if I don't want to reconstuct the waveform and just want to able to detect Highs and Lows? UART receivers for example, sample at 8 or 16 times the frequency F. Is that because they just want to detect High and Lows? They don't want to actually reconstruct the waveform, are just interested in certain points.

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  • \$\begingroup\$ the oversampling depends on quantization ratio max/min \$\endgroup\$ Sep 18 '18 at 17:13
  • \$\begingroup\$ @TonyEErocketscientist I don't understand. Can you elaborate? \$\endgroup\$
    – doubleE
    Sep 18 '18 at 17:19
  • \$\begingroup\$ If you have 10bit ADC with 1024 levels and you only need 2 then the sampling rate reduces by 1024 or conversely if Shannon's Law says 2fs for 1f rate but you need 1024 levels then you need 2*1024 sampling rate. But for phase on UARTs they use 16xf in order to sync the clock from start bit for 10 symbols with less error 10 symbols = 1 start+1stop + data or +1 for parity... but actually its 2*1024+1 * 2f \$\endgroup\$ Sep 18 '18 at 17:23
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You need to describe your "pulse train" in greater detail, but in general, your sample interval (period) needs to be strictly shorter than the shortest "high" or shortest "low" that can appear in your signal. Otherwise, you risk missing a high or a low altogether.

UARTs use high sample rates in order to deal with "sloppy" signals that might have significant noise or distortion. It also makes them more tolerant of speed errors between the two ends of the connection.

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  • \$\begingroup\$ I understand when you say 'sample interval (period) needs to be strictly shorter than the shortest Highs or shortest Lows'. That would ensure the highs and lows are not missed, but wouldn't be sufficient to actually reconstruct the pulse train. Am I correct? \$\endgroup\$
    – doubleE
    Sep 18 '18 at 17:17
  • \$\begingroup\$ Correct. That's what you said you wanted, right? \$\endgroup\$
    – Dave Tweed
    Sep 18 '18 at 17:19
  • \$\begingroup\$ yes, I was confused about the difference between full reconstruction and detecting high/lows for pulse trains. \$\endgroup\$
    – doubleE
    Sep 18 '18 at 17:20
  • \$\begingroup\$ But in actuality, you CAN reconstruct the waveform, if you know enough about its general characteristics. It's just a whole lot more difficult when your sample rate is close to the minimum rate. \$\endgroup\$
    – Dave Tweed
    Sep 18 '18 at 17:22
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The A in UART = asynchronous. This refers to the free running 16x clock generated by the receiver to look for the leading start bit edge then choose the middle of the bit using a 1x inverted clock( = bit rate) now synced to that edge. Since there is a small frequency difference, the clock phase slowly drifts early or late but no more than typically than 100ppm*10bits=0.1%.

This is done for each word with start and stop bit as a word frame check. This accommodates some bit shift due to signal distortion and clock frequency difference between the sender and receiver which are generally well within 100ppm.

Since it is already binary logic determined by the Rx threshold, which is the same as TTL @1.3V, while the signal is +/-V, there is no need to sample any more than this 16x f, nor any savings in silicon to sample less than this. So a UART 16x Clock has become a de facto standard. The exception is the highest bit rates, where an only 8x clock is available in some cases with a slight loss in the clock to data edge margin for error due to all the effects of bit phase shift.

If you were wanting to have synchronous data without start and stop bits then a PLL SERDES clock sync would be used which normally uses a clock at the same rate as the symbol rate. This is followed by a search for a unique frame sync pattern then it can decode the stream.

{ feel free to search any keywords, new to you, on the web.}

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  • \$\begingroup\$ What do you mean by "There is [not] any savings in silicon to sample less than this"? If I use a slower clock, then power consumption would be improved. I might also come with cheaper parts because of lower sample rate. \$\endgroup\$
    – doubleE
    Sep 18 '18 at 21:27
  • \$\begingroup\$ It can be derived from a slow Xtal already and is scaled down by counters so the savings are generally peanuts unless UARTs >1MHz but then signal integrity needs and BER demands. But higher data rates also need more phase margin which is reduced with an 8x clock. It depends on your signal. Going 9600 baud across campus , needed this in the 70's but doing 1Mbps over a short cable might not. \$\endgroup\$ Sep 19 '18 at 19:48
  • \$\begingroup\$ THe "certain points" are an estimate of the middle of bit based on the delay sending the start bit edge and noise ringing and other artifacts of mismatched cable impedance. So we are talking about quantization of start time not reconstructing the waveform . Have you read about eye patterns? \$\endgroup\$ Sep 19 '18 at 19:51

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