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In VHDL, are conditional IF statements evaluated when any signal in the process sensitivity list changes, or only if the signals are in the sensitivity list and appear as IF statement arguments?

I want to know if counted below is incremented only when enable, cnt_clk_cur, or cnt_clk_cur change state (assuming the IF statement evaluates true), or when any signal in the sensitivity list changes (and the IF statement evaluates true).

I am new to VHDL, so be nice. Any VHDL simulator recommendations are welcome.

begin

   process(clk, aclr, cnt_clk_last, cnt_clk_cur, cnt_clk, enable)

   begin
      if (aclr = '1') then                -- if aclr set all to zero
         counted <= (Others => '0');      -- clear counter
         cnt_clk_last <= '0';
         cnt_clk_cur <= '0';
      elsif rising_edge(clk) then         -- on an edge increment
         cnt_clk_cur <= cnt_clk_last;
         cnt_clk_last <= cnt_clk;
      if (enable = '1' and cnt_clk_cur = '0' and cnt_clk_last = '1') then
         counted <= counted + '1';        -- increment
      end if;
   end if;
   count <= counted;
   end process;

end behavioral;
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  • \$\begingroup\$ The cnt_clk_cur and cnt_clk_last. Are these present to detect a rising edge event on cnt_clk, a lower frequency strobe ? \$\endgroup\$ – JonRB Sep 18 '18 at 18:31
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    \$\begingroup\$ Just don't... Stick to a standard pattern (if you want to synthesise) and keep sensitivity list down to clk, aclr. And move that assignment to count somewhere else. (As it is, counted is missing from the sensitivity list and the other four signals in it are redundant. And the indentation is broken; if enable ... belongs a level further in. \$\endgroup\$ – Brian Drummond Sep 18 '18 at 20:28
  • \$\begingroup\$ @Brian Drummond Thanks... I've been looking at lots of examples and people appear to play fast and loose with the sensitivity list, with lots of redundant signals. \$\endgroup\$ – schadjo Sep 18 '18 at 21:00
  • \$\begingroup\$ This is why I was querying about the cnt_clk_last and cnt_clk_cur... was this added due to simulation observations or advised somewhere. Personally I keep clk and rst in teh sensitivity list. This stops any async nature to the code which could be trigged by a signal changing \$\endgroup\$ – JonRB Sep 18 '18 at 23:34
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The entire process will be evaluated if any signal in the sensitivity list changes.

The counted value needs to be in a clocked register, otherwise you create a combinational feedback loop. Therefore, the value of counted should only be changed on a rising clock edge.

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    \$\begingroup\$ And, you only need clk and aclr in the sensitivity list \$\endgroup\$ – CapnJJ Sep 18 '18 at 19:11
  • \$\begingroup\$ And counted is also reset using aclr (it can change when cleared as well as the rising edge of clk). \$\endgroup\$ – user8352 Sep 18 '18 at 19:29
  • \$\begingroup\$ As written, counted also needs to be in the sensitivity list, unless the likely half clock cycle delay on count is deliberate. \$\endgroup\$ – Brian Drummond Sep 18 '18 at 20:31
  • \$\begingroup\$ If you only add clk and aclr to the sensitivity list, you'll get a discrepancy between simulation and implementation with the matjority of synthesis tools, since they'll start by expanding sensitivity lists until each dependency is covered. \$\endgroup\$ – DonFusili Sep 19 '18 at 8:37

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