In VHDL, are conditional IF statements evaluated when any signal in the process sensitivity list changes, or only if the signals are in the sensitivity list and appear as IF statement arguments?
I want to know if counted below is incremented only when enable, cnt_clk_cur, or cnt_clk_cur change state (assuming the IF statement evaluates true), or when any signal in the sensitivity list changes (and the IF statement evaluates true).
I am new to VHDL, so be nice. Any VHDL simulator recommendations are welcome.
begin process(clk, aclr, cnt_clk_last, cnt_clk_cur, cnt_clk, enable) begin if (aclr = '1') then -- if aclr set all to zero counted <= (Others => '0'); -- clear counter cnt_clk_last <= '0'; cnt_clk_cur <= '0'; elsif rising_edge(clk) then -- on an edge increment cnt_clk_cur <= cnt_clk_last; cnt_clk_last <= cnt_clk; if (enable = '1' and cnt_clk_cur = '0' and cnt_clk_last = '1') then counted <= counted + '1'; -- increment end if; end if; count <= counted; end process; end behavioral;