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I'll be doing some analysis which requires at least cycle-accurate power estimations. From what I gather, the PowerPlay tool only calculates total power consumption.

I've also looked into Synplify, but from what I can tell the only benefit of this is that you are given finer-grain control over the synthesis process. Is it possible to use other Synopsys tools such as PrimePower or Primetime-PX to calculate cycle-accurate power on the Synplify synthesized designs? I don't think so, since there is no .cdl for the Altera device available - at least not that I know of.

Any suggestions on what tools/methodology can be used to estimate cycle-accurate power from the placed-and-routed netlist would be much appreciated! I'm using a CycloneIII FPGA.

-k

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You've indicated in your comments that your goal is to measure the effectiveness of countermeasures to differential power analysis attacks. As others have indicated, it will be difficult to impossible to get the level of information you'd need for a 100% detailed calculation from the FPGA vendors, since they'd just about have to send you copies of their mask sets. Even if you did have the data, doing a detailed simulation would take a lot of CPU time, since it's not just a digital sim anymore.

An easier way would be to create a development board optimized for differential power analysis. Route the power to the FPGA through a current sensing resistor with an amplifier right next to it, and a coax connection off the board to a scope. Remove as much supply capacitance downstream of the sensing resistor as is possible while still having the circuit operate. This mimics a practical attack, and gets data in seconds per measurement, instead of hours of simulation.

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You need to take a look at this paper. It talks about doing this kind of power estimation on a custom VLSI circuit for which they have all the details of its transistor-level implementation.

Unless you have a very close relationship with the FPGA vendor (Altera), I don't think you're going to get the level of detail on the internal circuitry of an FPGA that you'd need to do this kind of power estimation.

I've been designing FPGA applications for a number of years now, and I've never before seen the phrase "at least cycle-accurate" applied to FPGA power estimation. Just out of curiosity, what would be the next step beyond cycle-accurate?

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  • \$\begingroup\$ I suppose I was thinking instantaneous was beyond cycle-accurate. Thanks for the input, that was what I had suspected. Do you happen to know what information (if any) is available through PowerPlay? The documentation isn't too descriptive. I've seen an example of an XPower (Xilinx) report, which evidently gives some capacitance values for monitored signals, etc. but can't find such an example for PowerPlay. \$\endgroup\$ – kbarber Sep 7 '12 at 19:38
  • \$\begingroup\$ I guess my real point is that people who are really concerned about power consumption generally aren't using high-power FPGAs in their designs. That's why your question is surprising in this context. Can you give us some clue about where you're headed with this? Why do you need this level of detail for a Cyclone III-based design? \$\endgroup\$ – Dave Tweed Sep 7 '12 at 20:29
  • \$\begingroup\$ You have a point. The grounds for the analysis are really for an experiment - to find the data-dependency of the power consumption. I'm looking at countermeasures for power analysis attacks on FPGAs. Basically, I wanted to implement a couple of well-known countermeasures and attempt to mount an attack based on the simulated data and determine which countermeasure held up the best. Of course, I'm aware that this in itself is somewhat of a long shot - the more accurate the power models, the more likelihood that the data will actually give any insight and could be used for an attack. \$\endgroup\$ – kbarber Sep 7 '12 at 23:49
  • \$\begingroup\$ I did read that PowerPlay uses transistor-level proprietary models for the estimation - which gave me hope. However, if the data isn't cycle accurate it is no good. These attacks target specific instances of time (or cycles) where a particular operation within the cryptographic algorithm is being computed. I have some experience mounting attacks on simulated data on an ASIC implementation with Synopsys Nanosim, and I wanted to see if it was feasible from an FPGA perspective. If so, this gives FPGA designers some hope of gauging the amount of security they have. \$\endgroup\$ – kbarber Sep 7 '12 at 23:52
  • \$\begingroup\$ All of the gate-level primitives (such as LEs) are available in .db format for simulation-purposes - but, as I feared I think that anything past this is strictly proprietary. I think the only hope is to use PowerPlay, but I'm not sure if this will give me what I need or if there is another solution. Any insight or suggestions would be great! \$\endgroup\$ – kbarber Sep 7 '12 at 23:57

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