I am using SystemVerilog to write assertions in order to test the behavior of my design. In my design I have two clock :
the usual CLK_int
and another clock called I2C_IF_SCL_out
.
In the specification of my design:
SDA_Tick_shift
= 01 for one CLK_int period, 10 CLK_int
periods after falling edge of I2C_IF_SCL_out
.
What I am asking is can I use two clocks in my clocking block @(posedge CLK_int)
and @(I2C_IF_SCL_out)
?