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I am programming an Altera Cyclone IV using Verilog and Quartus II. In my design, I would like to use both edges of a clock so that I can do clock division by an odd factor with a 50% duty cycle. Here is a snippet of my code:

  always @(posedge low_jitter_clock_i or negedge low_jitter_clock_i or posedge reset_i) begin
    if(reset_i) begin
      fixed_clock <= 1'b0;
      divider_dummy <= 'b0;
    end else begin
      fixed_clock <= fixed_clock_next;
      divider_dummy <= divider_dummy_next;
    end
  end

Now when I compile this, Quartus II throws the following error:

Verilog HDL Always Construct error at adc_clocking.v(83): event control cannot test for both positive and negative edges of variable "low_jitter_clock_i"

How can I use both the positive and negative edge of a given clock in my design?

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When you assign to a register in an edge-sensitive always block, you're defining a flip-flop. FPGAs do not have flip-flops that can trigger on both edges of a clock.

In order to do what you want, you are going to need to have two separate always blocks, one for each edge of the clock, and then figure out a way to combine the outputs of the two blocks without creating glitches.

For example, one always block could contain your programmable divider. Design it so that the output duty cycle is less than 50% when given an odd number. Use the second always block (on the other clock edge) to delay the output of the first block by 1/2 clock, then OR the two outputs together. Disable the output of the second block for even divider values.

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  • \$\begingroup\$ The reason I want to use both positive and negative edges of the clock is to have a duty cycle of 50%. \$\endgroup\$ – Randomblue Sep 10 '12 at 8:31
  • \$\begingroup\$ Yes, I got that. My answer directly addresses that. I assumed you already know how to get a 50% duty cycle when the divider value is even. What isn't clear? \$\endgroup\$ – Dave Tweed Sep 10 '12 at 11:46
  • \$\begingroup\$ No dual-edge flip-flops? There is no inherent reason for this. It just turns out that nobody is making them (or at least nobody that we know of). As Martin points out, there is a CPLD that supports dual-edge flip-flops: xilinx.com/products/silicon-devices/cpld/coolrunner-ii/… \$\endgroup\$ – Philippe Sep 11 '12 at 15:04
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If this is for internal logic, you probably have to write much closer to the flipflops which are available. Except for Coolrunner-II I'm not aware of any programmable logic with inherently double-edge registers.

Therefore, you'll have to create two always blocks, one for the negedge and one for the posedge and combine their outputs with some combinatorial logic.

Or use a PLL to double the clock and then you can use conventional single-edged logic.

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I ended up implementing 50% duty cycle for odd division factors using the method described here.

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As Dave Tweed notes, unless an FPGA includes flip flop hardware which can operate on both edges of a clock, it will be necessary to write your own logic to implement the desired behavior using conventional single-edge flip flops. While there are a number of different ways that one may implement a circuit which behaves much like a double-edge flip flop, such circuits generally add some timing constraints which are different from those associated with flip flops.

For example, a simple approach is to have a module combining two 2-input xors and a pair of "T" flip flops (where the state of the input when a clock pulse arrives indicates whether that clock edge should toggle the output), one triggered by a rising edge and one triggered by a falling edge. The output of the module will be the xor of the flip flops' outputs, and the input to both flip flops will be the xor of the module's output and its input.

A circuit designed in this fashion will work essentially like a double-edge flip flop, though with longer setup and propagation times, but with an additional timing constraint. A normal flip flop which is not on a feedback path won't mind if the start of a clock edge has a bunch of runt pulses provided that the clock stabilizes at a valid level, and provided that the setup time constraint, measured from before the first runt pulse and the hold time and clock-active time constraints, measured from the time the clock pulse is stably active, are met. The behavior of the flip flop output will be undefined during the time the clock is unstable, but will be defined after the clock stabilizes. The double-xor-double-flop module would add the additional timing constraint that any clock edge which would change the output must be a safe distance from any other clock edge which might do so. Failing to meet that constraint, e.g. by having three clock edges in very close succession while the input doesn't match the output, could leave the output in an indeterminate or metastable state (note that scenarios involving an even number of edges are not a concern, since such scenarios would involve nothing but runt pulses; the three-edge case (or other odd-number cases greater than one) are a concern because there would be a valid pulse following the runt pulses.

An alternative circuit design would be to have the two flip flops as above, but feed their outputs into a multiplexer. This circuit would not be thrown into a bad state by runt pulses, and its clocking constraints would be the same as the underlying latches, but it would have the disadvantage that an output which was high and should remain (or was low and should remain low) so could glitch briefly on a clock edge. In some circuits that wouldn't matter, but in others, it would.

It would probably be possible for logic synthesis tools to implement double-edge flip flops automatically by analyzing what timing constraints have been specified as important, but doing so would be somewhat difficult. It would also increase the risk that a small change to a design might cause a major change in implementation and thus yield a significant and unexpected change in behavior.

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