As Dave Tweed notes, unless an FPGA includes flip flop hardware which can operate on both edges of a clock, it will be necessary to write your own logic to implement the desired behavior using conventional single-edge flip flops. While there are a number of different ways that one may implement a circuit which behaves much like a double-edge flip flop, such circuits generally add some timing constraints which are different from those associated with flip flops.
For example, a simple approach is to have a module combining two 2-input xors and a pair of "T" flip flops (where the state of the input when a clock pulse arrives indicates whether that clock edge should toggle the output), one triggered by a rising edge and one triggered by a falling edge. The output of the module will be the xor of the flip flops' outputs, and the input to both flip flops will be the xor of the module's output and its input.
A circuit designed in this fashion will work essentially like a double-edge flip flop, though with longer setup and propagation times, but with an additional timing constraint. A normal flip flop which is not on a feedback path won't mind if the start of a clock edge has a bunch of runt pulses provided that the clock stabilizes at a valid level, and provided that the setup time constraint, measured from before the first runt pulse and the hold time and clock-active time constraints, measured from the time the clock pulse is stably active, are met. The behavior of the flip flop output will be undefined during the time the clock is unstable, but will be defined after the clock stabilizes. The double-xor-double-flop module would add the additional timing constraint that any clock edge which would change the output must be a safe distance from any other clock edge which might do so. Failing to meet that constraint, e.g. by having three clock edges in very close succession while the input doesn't match the output, could leave the output in an indeterminate or metastable state (note that scenarios involving an even number of edges are not a concern, since such scenarios would involve nothing but runt pulses; the three-edge case (or other odd-number cases greater than one) are a concern because there would be a valid pulse following the runt pulses.
An alternative circuit design would be to have the two flip flops as above, but feed their outputs into a multiplexer. This circuit would not be thrown into a bad state by runt pulses, and its clocking constraints would be the same as the underlying latches, but it would have the disadvantage that an output which was high and should remain (or was low and should remain low) so could glitch briefly on a clock edge. In some circuits that wouldn't matter, but in others, it would.
It would probably be possible for logic synthesis tools to implement double-edge flip flops automatically by analyzing what timing constraints have been specified as important, but doing so would be somewhat difficult. It would also increase the risk that a small change to a design might cause a major change in implementation and thus yield a significant and unexpected change in behavior.