Consider the following data path of a simple non-pipelined CPU. The registers A,B, A1, A2, MDR, the bus and the ALU are 8-bit wide. SP and MAR are 16-bit registers. The MUX is of size 8×(2:1) and the DEMUX is of size 8×(1:2). Each memory operation takes 2 CPU clock cycles and uses MAR (Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally.

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The CPU instruction "push r" where, r= A or B has the specification



How many CPU clock cycles are required to execute the "push r" instruction?

A) 2

B) 3

C) 4

D) 5


Some say answer is A) some say B) and some say it's D)

I think answer is A) as SP is decremented locally; doesn't require any extra cycle. So, memory operation require 2 cycles.

This question is asked in GATE 2001 Exam,please help!

  • \$\begingroup\$ What part do you not know? \$\endgroup\$ Commented Sep 21, 2018 at 8:20
  • \$\begingroup\$ we have to consider only execution phase and not the complete inx cycle as mentioned in question. I think ‘r’ is stored at memory at address stack pointer currently is, this take 2 clock cycles SP is then decremented locally to point to next top of stack; doesn't require any clock extra cycle. So total cycles=2 am I correct? \$\endgroup\$ Commented Sep 21, 2018 at 8:24

1 Answer 1


The definition of "2 cycles per memory access" is a little vague, so I'm not sure if it's 3 cycles or 4 cycles. But here's how I feel that it goes:

Note: to help thought process, it's assumed here that the databus is driven at the clock falling edge and read at the rising clock edge, although it's not necessary to do so. It's just to help you think how the data flows.

Cycle 1: SP->DATABUS on the falling edge

Cycle 2: DATABUS->MAR on the rising edge; SP-1 -> SP on the rising edge; r -> DATABUS on the falling edge;

Cycle 3: DATABUS->MDR on the rising edge; Memory access cycle begins

Cycle 4: Memory wait state (is it necessary or is the addressing cycle 2 enough to satisfy 2 cycle memory delay?)

[Edit] The answers sheet here says the correct answer is B (3) so I guess the separate cycles for MAR and MDR satisfy the two cycle memory access requirement.


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