Consider the following data path of a simple non-pipelined CPU. The registers A,B, A1, A2, MDR, the bus and the ALU are 8-bit wide. SP and MAR are 16-bit registers. The MUX is of size 8×(2:1) and the DEMUX is of size 8×(1:2). Each memory operation takes 2 CPU clock cycles and uses MAR (Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally.
The CPU instruction "push r" where, r= A or B has the specification
How many CPU clock cycles are required to execute the "push r" instruction?
Some say answer is A) some say B) and some say it's D)
I think answer is A) as SP is decremented locally; doesn't require any extra cycle. So, memory operation require 2 cycles.
This question is asked in GATE 2001 Exam,please help!