I was given this inequality in logical circuits class and I can't figure out the reason behind it, and how can t_hold be negative. Is the condition relevant when t_hold is positive?
Your inequality doesn't make much sense to me, unless you are just trying to say that the setup time comes before the hold time.
The absolute values of the setup and hold time for a flip-flop cell are influenced by the relative delay of the data and clock signals inside the flip-flop cell. The actual master-slave flip-flop inside a flip-flop "cell" may have other gates around it for buffering or logic functions. If the internal delay path for the data input is significantly longer than the internal delay path for the clock then the hold time can be zero or negative, meaning that at the cell boundary you can remove data before the clock edge because the data at the actual master-slave flip-flop will still be valid for little while. This situation might occur if a couple gates were added to the data signal path to implement synchronous set and clear.