It seems that the flash memory on most microcontrollers that stores the assembly code is NAND flash, which is only accessible on a per-block basis. Does the CPU has to fetch an entire block to execute the code, or am I mistaken and is it made of NOR flash that is byte accessible?

The datasheet of the ATmega 186 says the following:

This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

The datasheet is not very clear what the technology is behind this "flash", but is seems to be different from the EEPROM that is used for the data, that has 10 times as many write cycles.

Edit: the possible suggested duplicate question and answers are about pipelining, not about the storage technology.

up vote 12 down vote accepted

No and Yes.

No, because as alex.forencich points out most MCUs use NOR flash. This greatly simplifies MCU architectures, as it allows them to fetch and begin executing a single instruction at a time. This is almost certainly how 8-bit AVRs, and PICs, and so on operate.

Yes, because some architectures use wider buses on their flash interfaces, pre-fetch, and/or multiple-issue to help overcome the latency of the underlying memory and improve overall performance. For instance, STM32F7 parts (Cortex M7) have a 128/256 bit bus between the flash controller and the underlying memory, and then a 64-bit AHB between the core and the flash controller. This means the flash controller retrieves four or eight instructions at a time, and the core can retrieve two instructions from the flash controller simultaneously. In this case, the core wants two instructions every cycle because it is uses a dual-issue pipeline, meaning that it can fetch and decode both instructions simultaneously, and in many cases dispatch both instructions to different processing units for simultaneous execution.

The flash controller may also pre-fetch additional instructions that the core has not yet requested, again to reduce the impact of flash latency. How far ahead the controller will pre-fetch, and whether it uses additional caching or other strategies where instructions are fetched in batches is highly architecture dependent.

Most microcontrollers actually use NOR flash, not NAND flash. And usually you can read whatever you like, it's usually only write and erase operations that are page-based. Unless you're using NAND flash that uses encoding/whitening, FEC, wear leveling, etc. In that case, the controller will do all that processing on a block or page basis.

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