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Explanation :

I have designed a PCB for motor control. On this PCB there is a power part and a logic part.

The power part is composed of MOSFETs, MOSFET drivers, hall sensor for current feedback and some protections (resistances, diodes…). The logic part is based on a Teensy (a logic board with an ARM Cortex-M3), some Phoenix connectors, voltage dividers, etc. There are also switching regulators to power the logic.

This is a two-layer board with no internal layers. The tracks for the power part are 6 mm width, those for the logic are 1 mm width. Clearance between tracks is at least 0.2 mm. The board has been tested with a 35 um copper thickness and except for some interferences, present on the logic when the motor draws current, the board is working well. Up to now these interferences are software corrected (median filter).

I want then to make the board with a 70 um copper thickness, to be able to pass more current to the motor.

Questions and ideas:

What will happen to interference, if I change from a 35 um copper thickness to a 70 um one (for all the board, so power and logic will be changed to 70 um)?

I think they will increase because the sensitivity of a track to interference, depends on its section and length (wider and longer mean more subject to interference for me). True?

Do you think I need to increase my clearance? If yes, to which value?

I think it also depends on the MOSFET frequency commutation compared with track length (resonance…).

Any help will be greatly appreciated!

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You will have significantly more interference, but it has nothing to do with the increased copper thickness, and everything to do with the increased current. In other words, while there are both capacitive and inductive coupling mechanisms at work, the change you are making to the capacitance is completely negligible.

By all means, increase the copper thickness, but also redesign the isolation between the power circuits and the digital circuits.

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  • \$\begingroup\$ Thanks for your answer :) I didn't had the experience to know that this change is completely negligible in term of noise. Do you think that I can reduce interferences by reducing logic track width (from 1mm to 0.5mm for example) ? \$\endgroup\$ – Orbs Sep 23 '18 at 15:13
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    \$\begingroup\$ No, the logic track width has little to do with the coupling. You need to increase the clearance between logic circuits and power circuits, which will reduce both inductive and capacitive coupling between the two. How much voltage are you dealing with on the power side? That alone will probably dictate greater than 0.2 mm (8 mil) clearance between the two. I would want to see several mm. \$\endgroup\$ – Dave Tweed Sep 23 '18 at 15:19
  • \$\begingroup\$ I'm dealing with 24V for the power side (and a mix of 3V3, 5V, 15V and 24V for the logic side). Between the logic track there is a 0,2mm clearance but between a track from the logic side and a track from the power side there is at least 1,35 mm clearance. Maybe not enough ? \$\endgroup\$ – Orbs Sep 23 '18 at 15:28
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    \$\begingroup\$ You didn't say that in your question. And no, it may not be enough, especially when you consider transients that might occur on the power side. Do you have any inductive loads? How much power overall are we talking about anyway? \$\endgroup\$ – Dave Tweed Sep 23 '18 at 15:31
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    \$\begingroup\$ Can you route the high-current return paths, so they are underneath the high-current output paths? Reducing the area of a high-current loop is one of the two ways to reduce magnetic field transient interference; the other way is to slow down the edges, but that likely increased heat losses. \$\endgroup\$ – analogsystemsrf Sep 23 '18 at 16:30
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500V/mm to 1kV/mm track gaps is for arc protection or surface dielectric breakdown. The real problems include crosstalk from noise. Motors have a lot of high-frequency commutation noise mainly due to high switched current to rise time ratio or dI/dt = V/L but coupling can be both inductive or capacitive.

You are describing the PC layout needs for EMC design, which can fill a few books and is a pretty complex subject itself so I won't attempt that here. There are many factors including mutual inductance, mutual capacitance and load impedance.

Fortunately, there are free PCB design tools and many Rules of Thumb (expert advice on how) to avoid and choose better ways to prevent interference. , there are easy ways to design low impedance tracks with a nearby ground in order to attenuate coupling from the coupling of a slightly farther away from a high current signal for a high dI/dt or dV/dt switched supply or switched motor load.

In order to use these tools, you must understand the simple relationship of a resistance divider to attenuate a signal then equate this to the effective inductance and capacitance of any track to an adjacent track or ground track or a ground plane.

The rule of thumb is keep your friends (Ground) close and stay away from enemies ( high current pulses) or at least put a good ground track or better a ground plane between them.

The model of a signal and noise on two adjacent tracks

schematic

simulate this circuit – Schematic created using CircuitLab

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    \$\begingroup\$ Thanks for your detailed answer. I will dig into EMC rules books and check the soft. Yet an other question: when you said " at least put a good ground track or better a ground plane between them." do you mean between two high current pulse tracks or between a high current pulse track and a logic track ? \$\endgroup\$ – Orbs Sep 23 '18 at 17:43
  • \$\begingroup\$ High current and its return path ought to be paired close with gnd tracks on either side to avoid inductive loops. over a gnd plane is better if routed carefully to source low ESR DC caps. For sensitive high impedance sensors, gnd between other signals and away from high current dI/di even right angles. Logic is lower Z <=50 Ohms still needs consideration. The longer the cable, the greater the CM noise so Ferrite CM Pi filters are often used for BLDC and stepper and DC motors on longish cables. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 23 '18 at 17:49

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