Trying to find what is the clock-to-output delay for registers inside EP4CE6E22C6.
Have looked through the 3 Cyclone IV handbooks searching by delay but have not found any values specified. All the delays specified appear to be input/output delays, not internal delays.
If with a 100MHz clock I'm latching data into a reg at the falling edge will this input register on the output 5ns later on the rising edge?
//clk - 100MHz reg r1; reg r2; always @(negedge clk or posedge clk) begin r1 <= in_data; r2 <= r1; end