# Altera Cyclone IV clock-to-output delay

Trying to find what is the clock-to-output delay for registers inside EP4CE6E22C6.

Have looked through the 3 Cyclone IV handbooks searching by delay but have not found any values specified. All the delays specified appear to be input/output delays, not internal delays.

If with a 100MHz clock I'm latching data into a reg at the falling edge will this input register on the output 5ns later on the rising edge?

//clk - 100MHz
reg r1;
reg r2;

always @(negedge clk or posedge clk)
begin
r1 <= in_data;
r2 <= r1;
end

• It varies depending on where the output is routed to. Load your code into Quartus, run a timing analysis, and you can answer your own question. – Jules Sep 23 '18 at 16:45
• What about internally for a flip-flop, ignoring outputs? I may run the timing analysis some day, don't have enough knowledge how to use it right now. – axk Sep 23 '18 at 17:04
• You really, really need to constrain your design and run the timing analyser. Routing delays are usually more significant then logic propagation delays, and if you do not at least constrain the thing the place and route stage has no hints as to witch paths are critical. Incidentally, are you sure that clocking on both edges will actually work? This is HIGHLY device specific and frankly slightly uncommon. – Dan Mills Sep 23 '18 at 18:43
• I'm not actually clocking on both edges, this is just an example, I've defined my process on the falling edge and the SDRAM is sampling on the rising edge this way I my understanding the signals will be more stable when the SDRAM is sampling them. Making a very basic SDR SDRAM controller with a test bench for a frame buffer, will see if it works straight away on the real device, if it doesn't will get into the timing constraints, looks like too much stuff to grasp at once. – axk Sep 23 '18 at 20:14