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I'm designing an inverter for trapezoidal control of a 500W BLDC motor, using DRV8301 for the gate driver. My switching frequency is 10Khz, Vdd is 48V, and Imax=20A. I've been trying to calculate the power dissipation in the FET's based on a few preliminary FET choices. One FET is the STB46N30M5. This FET is overkill for the application, but even with a lesser FET, the switching losses are huge - larger than the conduction losses. My calculation was as follows: $$ Q_\mathrm{tot} = Q_\mathrm{GS}+Q_\mathrm{GD} = 95\,\mathrm{nC} $$ $$ R_\mathrm{ds} = 40\,\mathrm{m}\Omega $$ DRV301 average gate current is 30mA, divided by 6 MOSFETs: $$ I_\mathrm{gate} = \frac{30\,\mathrm{mA}}{6} = 5\,\mathrm{mA} $$

$$P_\mathrm{sw} = \frac{1}{2}V_\mathrm{dd}I_\mathrm{o}f_\mathrm{sw}\frac{Q_\mathrm{tot}}{I_\mathrm{gate}}$$ $$P_{sw} = \frac{1}{2}\times48\,\mathrm{V}\times20\,\mathrm{A}\times10\,\mathrm{kHz}\times\frac{95\,\mathrm{nC}}{5\,\mathrm{mA}}= 91.2\,\mathrm{W}$$ $$P_\mathrm{con} = I_\mathrm{ds}^2R_\mathrm{ds}=16\,\mathrm{W} $$

The switching time is 19uS, which is quite long. Possibly using 5mA is incorrect, but using peak drive current doesn't seem logical to me.

$$ t_\mathrm{r} = \frac{Q_\mathrm{tot}}{I_\mathrm{gate}} = 19\,\mu\,\mathrm{s} $$

Do these values seem reasonable? Do I just need to find a beefier gate driver? Thank you for any tips.

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  • \$\begingroup\$ With numbers above average gate current is around 10kHz×95nC=950uA each FET. \$\endgroup\$ – carloc Sep 24 '18 at 1:06
  • \$\begingroup\$ Both average and gate driver capability currents do not rule switching times, you should use actual gate peak current instead. What is the app note you base your design on? \$\endgroup\$ – carloc Sep 24 '18 at 3:50
  • \$\begingroup\$ Hi Carloc I did a more in-depth calculation using (application-notes.digchip.com/070/70-41484.pdf). Since I don't know what the actual peak current is I suppose I don't have enough information. \$\endgroup\$ – Alexander Villa Sep 24 '18 at 17:26
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    \$\begingroup\$ Hi Alex, great, Infineon AN is indeed a good one. You'll find gate currents expressions at bottom of pages 8 and 9, otherwise you might also just use rise and fall times reported on datasheet.This calculations are always kinda ballparking, do not get stuck on decimals. Finally I'd rather go for some much lower RDS(on) FETs, I believe 16W each just for conduction is really too hard to be cooled down. \$\endgroup\$ – carloc Sep 24 '18 at 23:32
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    \$\begingroup\$ Yes you got it :) it's a degree of freedom to be used in design \$\endgroup\$ – carloc Sep 25 '18 at 1:04
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Even with high switching current, the average gate current will be quite low, essentially zero except during each instance of switching. Calculating switching time is always tricky, because of the way parts are specified. The driver max current values for this part are measured at 2V (source) and 8V (sink), and the minimum gate drive voltage is not specified at this current but at a lower current. TI does not give any curves for this part, only a few discrete points. The FET looks reasonable with its input and reverse transfer capacitance values. So, an accurate calculation of switching time is not really feasible.

Having sais this, you should expect switching times in the hundreds of nanoseconds rather than the 19 uS you have estimated. You can adjust the switching time with a series resistor on the gate drive, although this may not be needed since the part has built-in dead time. Make the FET traces wide and short, including the gate, to avoid inductance.

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  • \$\begingroup\$ Thank You! I did a more in-depth calculation of switching time before seeing your comment using (application-notes.digchip.com/070/70-41484.pdf), however the issue of not knowing what the current waveform looks like remains an issue. I'll keep in mind that switching time should be in hundreds of nano-seconds, so thank you for that. \$\endgroup\$ – Alexander Villa Sep 24 '18 at 17:23

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