Verilog - Can you `define a bit slice?

Question

Can you define a bit slice in Verilog?

For example, is this possible:

`define opcode 5:3  // is this possible?

reg [ 7:0 ] a, b;

...

if ( a[ `opcode ] == someValue )  // a[5:3]

    doStuff

if ( b[ `opcode ] == someValue )  // b[5:3]

    doStuff

Answer 1

You can `define almost any text you want. You would have to use a[`opcode] with the backtick.

SystemVerilog gives you some other options.

The let construct declares a name for an expression.

let opcode = a[5:3];
...
if (opcode==someValue)

You can use a packed struct.

struct packed {
   logic [1:0] field1;
   logic [2:0] opcode;
   logic [2:0] field2;
} a;

Now you can refer to a.opcode as the same as a[5:3].

Answer 2

Yes, you can.

But it's probably cleaner and easier to simply break the register into fields using wires:

wire [2:0] a_opcode = a[5:3];

if (a_opcode == someValue) ...

How many different registers are you going to be extracting opcodes from?