Can you define
a bit slice in Verilog?
For example, is this possible:
`define opcode 5:3 // is this possible?
reg [ 7:0 ] a, b;
...
if ( a[ `opcode ] == someValue ) // a[5:3]
doStuff
if ( b[ `opcode ] == someValue ) // b[5:3]
doStuff