I have a CPU with a 32 bits data bus and a 21 bits address bus. I would like to know how much storage I can connect to this CPU directly.

Does this depend on the address bus width, because I can just address 21 bits of these 32 bits data or how does this work?

  • \$\begingroup\$ 2097152 bytes. Assuming no other regions of the 21 bit range are allocated. It would help if you can share what part you are using. \$\endgroup\$ – Jeroen3 Sep 24 '18 at 12:32
  • \$\begingroup\$ I cannot decide, either 2097152 or 8388608 bytes. \$\endgroup\$ – Alexander von Wernherr Sep 24 '18 at 12:36
  • \$\begingroup\$ @Jeroen3 I disagree. See my answer. \$\endgroup\$ – dim lost faith in SE Sep 24 '18 at 13:04

It depends on what you mean by 21 address bits:

  • If it means that the address registers have 21 bits (size of the CPU internal address bus), then it typically means the addressable space is 2^21 bytes, because on the vast majority of CPUs, the address has a byte granularity. In this case, it also means that, if you have a 32 bit external data bus, there will likely be only 19 lines on the external address bus.
  • If 21 bits is the size of the external address bus, the answer is much more likely 2^21*4. Otherwise, it means that the adjustments for aligned access have to be made by some external logic, which would mean quite a lot of glue logic chips required, making the design overly complex. I have never seen cases where this glue logic is not embedded in the CPU itself.

Since the question mentions 32 bit data bus, which typically refers to the external data bus, it seems logical to expect that the 21 address bits also refer to the size of the external address bus. So I would opt for the second option without hesitation.

  • \$\begingroup\$ Indeed, 2097152 words is a better explanation. Since nothing is known about the word size of the chip. \$\endgroup\$ – Jeroen3 Sep 24 '18 at 13:50

As Jeroen3 says, 2,097,152, which is 221.

Even though the system is 32 bits, normally the addresses are set by byte, meaning you have this many bytes available to be addressed. So you can access each single byte within this region, thus an alignment of 1 byte.

Preferred answer (see Dave Tweed's comment below):

However, I can imagine there exist CPUs which use 32-bit addressing, which means 221 × 4 (bytes) = 8,388608 bytes. This way you can only access addresses with an alignment of 4 bytes.

  • 2
    \$\begingroup\$ Even if a 32-bit system is byte-addressable, it is not always necessary to bring out the low-order two address bits to the physical bus. So 8 MB is actually the preferred answer, unless the OP provides additional information. \$\endgroup\$ – Dave Tweed Sep 24 '18 at 12:48
  • \$\begingroup\$ @DaveTweed thanks for the clarification, I adapted the answer according to your remark. \$\endgroup\$ – Michel Keijzers Sep 24 '18 at 12:55

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