I found a great application note on building a multi-cell lithium battery charger with cell balancing.


The great thing about this one is that you implement the charging algorithms yourself on an on-board MCU. If you already have an MCU and knowledge of the charging sequences of lithium batteries, this can be a cheaper option than buying a standalone chip that does the algorithms for you.

I understand the functionality of the circuit and what it's doing. But I had a question about a part of the circuit. Specifically the balancing MOSFETs and how they are driven.

Given the below schematic: enter image description here

See that Q4-Q7 are the balancing FETs that turn on to discharge a cell that is out of balance.

These FETS are driven by a GPIO pin on the MCU with a PWM signal. The app note says the following:

"The cell-balancing MOSFETS Q4-Q7 should be controlled at appropriate levels. One possible way to do this is to create a count level translator using a PWM signal coupled with AC. The rectification of the translator forms the DC level to turn on the corresponding transistor. This design uses one pulse width modulator, PWM_BAL. PWM_BAL has been placed in DCB12 and output to the demultiplexer, which is built around software-configurable global output buffers. PWM_BAL is configured in the software as a 4-bit PWM with a switching frequency near 115 kHz. When a MOSFET is turned on, the internal output buffer is enabled, passing the PWM signal to the rectifier. The diode networks D7-D8 are used for PWM signal rectification with amplitude doubling. The rectifiers’ low-pass filters consist of resistors R10, R14, R18, and R24 along with the MOSFET gate-channel capacitance. "

I don't quite understand this part of the circuit. The PWM signal is rectified and filtered via the 1Meg resistor and the MOSFETs gate capacitance. I would love to simulate this in TINA spice.

The FET they have is the BS170FTA and has the following gate threshold: enter image description here

You need 3V just to get 1mA of drain current. We want closer to 35mA to load the cell to drop it's voltage for balancing. So if the GPIO outputs a 3.3V PWM signal, it has to drive the gate much higher to get the 35mA of drain current. Unfortunately the datasheet does not have a VGS ID curve in it.

Would someone be able to explain how this little circuit works? I need this understanding to design my own and choose the proper components. Since it seems like the parasitics of the components are playing a key role here.

Below is a zoomed in picture of the circuit of interest. enter image description here

Thanks for the help.

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    \$\begingroup\$ It says "The diode networks D7-D8 are used for PWM signal rectification with amplitude doubling." Then it means that it produces near 6V. IMO it starts conducting very good below Vgs th, but you can choose some different transistor with a decent datasheet. \$\endgroup\$ Sep 24, 2018 at 22:20
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    \$\begingroup\$ @MarkoBuršič - I'm afraid that you do not get voltage doubling. You will only get the peak to peak voltage at the output. It is actually worse than that as the voltage drop from the diodes need to be accounted for. If the GPIO outputs 3.3v peak to peak the output voltage will be about 2.3V. The reason the circuit worked for the designer is probably that a typical FET has a threshold voltage that is much lower than the worst case 3V, maybe 1-1.5V and so can get turned on adequately. \$\endgroup\$ Sep 24, 2018 at 22:46
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    \$\begingroup\$ @Marko Buršič, but I'm trying to understand how/why this doubles it. I tried to simulate this with a 115k Hz 50% duty cycle PWM signal and it did not get anywhere near 6V. \$\endgroup\$ Sep 24, 2018 at 22:47
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    \$\begingroup\$ @guitardenver - You will not get double the 3.3v. The output voltage of a 'Voltage Doubler" rectifier is approximately the peak to peak voltage of the AC input. Normally this is used with 50/60Hz AC power input where the RMS or Peak voltage is quoted, not peak to peak and so seems to double the voltage relative to a simple half wave or bridge rectifier. \$\endgroup\$ Sep 24, 2018 at 22:52
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    \$\begingroup\$ Note that if you do want double or more voltage at low currents, you can use a voltage multiplier instead of a voltage doubler. For tiny loads they're not horrible. \$\endgroup\$
    – K H
    Sep 25, 2018 at 0:51

2 Answers 2


Let's start with the VGS ID curve. Fortunately, the schematic lists the part number for the MOSFET (BS170), so, from the datasheet:

enter image description here

Notice that at 3.0V, the MOSFET is already conducting 50-100mA typically. Note that 3V is listed as the "maximum" VGS(th), meaning the "typical" threshold voltage is probably somewhat lower.

Let's look at the circuit. As Marko Bursic's comment points out, it is used for "PWM signal rectification with amplitude doubling". Applying a PWM square wave excites an AC current passing through C5. When the current is positive (to the right), D7 conducts, charging the parasitic gate capacitance Cgs of the MOSFET. When the current is negative (to the left), D8 conducts instead, preventing the negative current from discharging Cgs. Meanwhile, R1 is constantly discharging Cgs, and as soon as the PWM waveform is turned off, Vgs will begin decaying and the MOSFET will eventually turn off.

But wait! What happened to the "voltage doubling"? Well, it turns out that a "voltage doubler" produces a DC value that is 2X the peak value of an AC waveform. In our example, the AC waveform is 3.3V peak to peak, or 1.65V peak. Which means the "doubled" voltage is still just 3.3V, less the diode drop.

So in conclusion, it is theoretically possible that a worst case combination of high diode drop and high VGS(th) could prevent a certain channel of this circuit from working. If the circuit is intended to work with 3.3V PWM, you're probably fine as the designer probably tested quite a few of these. If the designer tested with 5V PWM instead, you may eventually hit a problem - but my guess is, you'll still be fine.

Quick aside: "PWM" typically implies that the duty cycle of the signal is a control input - that's not the case here. The current through the MOSFET is totally independent of duty cycle! The only purpose of the so-called PWM is to produce an AC waveform.

enter image description here


Pager 21 onward in your linked App Note shows how it works.

A 5V 60% *est duty cycle square wave to series cap negative diode clamp supplies a 4.3=Vgs to enable the 100 Ohm series R to appear as 100/d.c.=160 ohms average if the differential battery charge needs to be bypassed by applying this “PWM modulated” shunt resistor across each cell as required until the CV string charge current reaches the 10% of CC charge current threshold and cuts off.

However they also show Vcc=3.3 which requires lower Vt FETs.

Thus the balancing is limited to low currents after CC phase , I believe when the current is declining in CV phase of the charge cycle.

This is less efficient that a switched inductor which can stored the current during bypass, but then that method is already patented.

It also limits the percentage of cell mismatch due to the power dissipation during CC cannot be entirely bypassed with 4.2V/100 Ohms or 42mA. So it is only for very small differences in cell capacity. But this method will extend the string life but how much depends on initial conditions and life temperature stresses.

  • \$\begingroup\$ Who does not understand my correct answer needs to ask a question to clarify -1. The two diodes act as negative clamp and forward rectifier respectively.period. It is obvious. And fundamentals nd quite different from arrangement for a doubler. \$\endgroup\$ Sep 25, 2018 at 12:45
  • \$\begingroup\$ A doubler takes Vp+/- and doubles the Vp to a DC level this restores Vp- near 0V then rectifies the positive PW modulated resistance of the series 100 R. \$\endgroup\$ Sep 25, 2018 at 12:52
  • \$\begingroup\$ Still one silent idiot -1 \$\endgroup\$ Sep 25, 2018 at 13:23
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    \$\begingroup\$ +1 Offsetting the silent idiot :-) \$\endgroup\$
    – Russell McMahon
    May 29, 2019 at 2:08

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