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I am reading wikipedia page of TRIAC. While reading, I got struck with holding and latching current definition. They look similar to me but the wiki says they are different. Find the wiki screenshot below:

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When a gate signal is applied to a triac/SCR/thyristor it won't latch until the main current flowing through the device has reached the "latching" level. It will conduct if the gate signal is sufficient but, if you remove that gate signal before the latching current level has been reached then it will stop conducting.

Once latched, the gate signal can be removed and it will stay conducting (latched) until the current falls to the level called the holding current. Clearly the "holding" current is less than the latching current.

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    \$\begingroup\$ Precise. This is what I was looking for. \$\endgroup\$
    – abhiarora
    Commented Sep 25, 2018 at 15:45
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    \$\begingroup\$ Gratitude is always appreciated. \$\endgroup\$
    – Andy aka
    Commented Sep 25, 2018 at 15:46
  • \$\begingroup\$ A good drawing says more than 1000 words. \$\endgroup\$ Commented Sep 25, 2018 at 17:20
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Latching depends on current gain to create 2 Vbe drops then positive feedback of SCR holds them until net saturated hFE which is lower thus no external current input to stay held, rather load current or zero crossing v, to get unlatched.

When current is reduced such that the positive feedback cannot sustain the latch with some reduce load current due to lower voltage drop.

This depends on the internal bias R used for positive feedback and the load current often with a hFE of about 20% of linear hFE.

In simple terms it is different due to external trigger currents and internal self latching bias current ratios

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