in the verilog code below:

module mem_try(
clk,
data_in,
rd,
wr,
data_out
);

input [data_width-1:0]data_in;
input clk,rd,wr;
output reg [data_width-1:0]data_out;
reg[data_width-1:0]ram[ram_depth-1:0];//ram variable decalaration
assign write_only =wr&~rd ;

always@(posedge clk) begin

if(write_only) begin
end

end

end
endmodule


After synthesis I get the following error:

[Synth 8-3331] design mem_try has unconnected port addr[31](30 more like this)

and a distribute ram is formed.

Can anyone point out the mistake and how a bram can be inferred?

• please indent all of the code by 4 more spaces so that it shows up as code .... you can also select the code text and click {} button – jsotola Sep 26 '18 at 5:12
• I'm not sure if this is the cause of the error, but it is usual to have the number of bytes in a ram specified as [0:size-1] but you have this reversed. – Jules Sep 26 '18 at 11:01
• @Jules you can specify it either way. What's more interesting is the attempt to make a 16GB array in in distributed RAM. – Tom Carpenter Sep 26 '18 at 17:58
• any suggestions how can i infer a block ram ? what changes do i need to do . If i chnage the addr_length and data_width to 8 ,(0.50)BRAM is inferred . – Shubham Choudhary Sep 27 '18 at 4:58