0
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in the verilog code below:

module mem_try(
     clk, 
     addr,    
     data_in, 
     rd,
     wr,  
     data_out
    );

      parameter addr_length=32,data_width=32,ram_depth= 1 << addr_length;
      input [data_width-1:0]data_in;
      input clk,rd,wr;
      input [addr_length-1:0]addr;
      output reg [data_width-1:0]data_out;
      reg[data_width-1:0]ram[ram_depth-1:0];//ram variable decalaration 
      assign write_only =wr&~rd ;
      assign read_only =~wr&rd ;

      always@(posedge clk) begin

      if(write_only) begin
         ram[addr]<=data_in;
      end


      if(read_only) begin    
        data_out<=ram[addr];
      end

      end         
endmodule

After synthesis I get the following error:

[Synth 8-3331] design mem_try has unconnected port addr[31](30 more like this)

and a distribute ram is formed.

Can anyone point out the mistake and how a bram can be inferred?

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  • 1
    \$\begingroup\$ please indent all of the code by 4 more spaces so that it shows up as code .... you can also select the code text and click {} button \$\endgroup\$ – jsotola Sep 26 '18 at 5:12
  • \$\begingroup\$ I'm not sure if this is the cause of the error, but it is usual to have the number of bytes in a ram specified as [0:size-1] but you have this reversed. \$\endgroup\$ – Jules Sep 26 '18 at 11:01
  • 3
    \$\begingroup\$ @Jules you can specify it either way. What's more interesting is the attempt to make a 16GB array in in distributed RAM. \$\endgroup\$ – Tom Carpenter Sep 26 '18 at 17:58
  • \$\begingroup\$ any suggestions how can i infer a block ram ? what changes do i need to do . If i chnage the addr_length and data_width to 8 ,(0.50)BRAM is inferred . \$\endgroup\$ – Shubham Choudhary Sep 27 '18 at 4:58
0
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Looks like you should be able to infer a block RAM with that. Not sure if that read /write exclusive logic will trip anything up. I wuld recommend setting the address width much smaller, maybe something between 8 and 16, otherwise the synthesizer is not going to be happy.

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