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I'm facing a weird problem. I have written an UART and a FSM. This design just print some text on the screen automatically, just after loading the bitstream. The problem is: when I load the bitstream, the text is printed withour error, but when I press the reset button to get that text printed again, what I see (in most of the cases) are strange and illegible characters.

Do you know what could be the problem?

enter image description here

Link to my current design: https://github.com/salcanmor/SRAM-tester-for-Cmod-A7-35T

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    \$\begingroup\$ Is your baud rate the same amount as your device's specified recommendation? \$\endgroup\$ – user103380 Sep 26 '18 at 23:45
  • \$\begingroup\$ If you have a DSO, capture the beginning of the 1st (good) response, and compare this to the beginning of the 2nd (garbled) response. I suspect you'll see a difference. Perhaps the TX line is held in an illegal state during reset, such that when it comes out of reset and immediately tries to transmit, the receiver is off by some number of bits. \$\endgroup\$ – rdtsc Sep 27 '18 at 1:03
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    \$\begingroup\$ Is your buffers cleared before each transmit? Else they could be sending garbage data. \$\endgroup\$ – user105652 Sep 27 '18 at 1:07
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    \$\begingroup\$ Did you debounce the button ? most switch have a bounce effect, it's possible that your FPGA actually reset numerous time which interrupts data during transfer. Try to add a 50ms timer before starting to send data / add a R-C filter on the reset line. \$\endgroup\$ – Damien Sep 27 '18 at 6:01
  • \$\begingroup\$ Maybe after reset the UART must be initialized/reconfigured? \$\endgroup\$ – Nazar Sep 27 '18 at 12:39
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Your circut appears out of sync after reset. You must review synchronization techniques you use, and protocol you use (start/stop and other control bits).

If you carefully look at the correct and incorrect output, you will see that in correct output you have 50 - characters, in incorrect you have about 50 j characters

- code is 2d = 0010 1101

j code is 6a = 0110 1010

You can see that bitstream is the same, just shifted 3 bits left.

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  • \$\begingroup\$ Seems unlikely, The communication starts with a start signal, there isn't specific timing to start a communication. \$\endgroup\$ – Damien Sep 27 '18 at 13:32
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    \$\begingroup\$ You can not state that without considering bitstream. But you can not deny that coincidence of bits is in place. \$\endgroup\$ – Anonymous Sep 27 '18 at 13:46

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