I have been using a Tiva C microcontroller (TM4C1294NCPDT) as master to communicate with 6 SPI devices (slaves). The SPI clock is 8 MHz with 1.5 ns rise time. My idea is depicted bellow.

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My design do not allow chaining devices, thus, I need to attach a separated CS line to each slave. The PCB I have designed is depicted bellow

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This is a 2-layer board with signal and power at the top and a solid ground plane at the bottom. The bus lines is 8 mil wide and there are no relevant stubs (pass beneath the pads). This board with the slave devices is connected to MCU evaluation board through 2.54 mm headers.

My worry is related to length of the SPI bus tracks on the PCB, which we can see, is > 55 mm long, and because the same SPI bus is attached to multiple devices, which can cause reflections due to impedance mismatch. I never connected multiple SPI devices to a single SPI bus before, just one-to-one, and I have no much knowledge about transmission line techniques. My question is: Should I have to consider some termination scheme at the bus ? I read that the series termination should be used when just one slave is attached to the bus (one-to-one). For one-to-many (master and slaves) either parallel or AC can be used at the end of the SPI lines to do the trick, but I'm not confident about the need to use termination in my case and if necessary, which is the proper scheme to use and in which lines.

  • \$\begingroup\$ During one of the lectures of signal integrity, I remember that the professor told us: "anything below 20Mhz basically DC, so you can ignore terminations and line impedance". \$\endgroup\$
    – Lelesquiz
    Commented Sep 27, 2018 at 15:16
  • 1
    \$\begingroup\$ @Lelesquiz Then your lecturer shouldn't be lecturing about SI (or EMI). These days with transistor sizes shrinking and rise/fall-times plummeting to below a ns, signal frequency is much less the contributor than the effective frequency content (harmonics) caused by the rise/fall-time. \$\endgroup\$ Commented Sep 28, 2018 at 7:17

1 Answer 1


Rather than worry about controlled impedance, matched terminations, reflections, and all that, what you should do is increase the rise and fall times of your signals.

You have a 125 ns clock period. A rise and fall time of 10-12 ns on the data signals and 6-8 ns on the clock will have negligible impact on your timing margins, but dramatically reduce the likelihood of any issues from impedance mismatches.

Since the SPI bus doesn't have bidirectional I/O's, you can do this by just adding a series resistance at every output driver. Ideally you'd calculate the capacitance of each driven line (at least roughly), and calculate the resistance to give the rise-time you want. Or you can pick a value between maybe 5 and 50 ohms, and adjust it later if you have problems or if measurements on the actual board show too fast or slow rise times.

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    \$\begingroup\$ I wouldn't have thought of this as a solution, but on thinking about it I really like it. Change the R to with the C give you the rise time you want. Elegant! \$\endgroup\$
    – zeta-band
    Commented Sep 27, 2018 at 21:28

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