I have been using a Tiva C microcontroller (TM4C1294NCPDT) as master to communicate with 6 SPI devices (slaves). The SPI clock is 8 MHz with 1.5 ns rise time. My idea is depicted bellow.
My design do not allow chaining devices, thus, I need to attach a separated CS line to each slave. The PCB I have designed is depicted bellow
This is a 2-layer board with signal and power at the top and a solid ground plane at the bottom. The bus lines is 8 mil wide and there are no relevant stubs (pass beneath the pads). This board with the slave devices is connected to MCU evaluation board through 2.54 mm headers.
My worry is related to length of the SPI bus tracks on the PCB, which we can see, is > 55 mm long, and because the same SPI bus is attached to multiple devices, which can cause reflections due to impedance mismatch. I never connected multiple SPI devices to a single SPI bus before, just one-to-one, and I have no much knowledge about transmission line techniques. My question is: Should I have to consider some termination scheme at the bus ? I read that the series termination should be used when just one slave is attached to the bus (one-to-one). For one-to-many (master and slaves) either parallel or AC can be used at the end of the SPI lines to do the trick, but I'm not confident about the need to use termination in my case and if necessary, which is the proper scheme to use and in which lines.