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On PIC micro controller UART, Baud rate was set to 38400 (No parity,, 8 data bits),

*************UART 1 configuration********* 
IFS0bits.U1RXIF = 0;

IFS0bits.U1TXIF = 0; 

IEC0bits.U1RXIE = 1; 

IEC0bits.U1TXIE = 0; 

U1MODEvalue = 0b1000000000001000; 

U1STAvalue = 0b0000010000000000; 

U1BRG = 103; 

U1MODE = U1MODEvalue; 

U1STA = U1STAvalue;

Device connected to uC is working fine; they have healthy communication. But I was measuring the baud time of my data, and I observed that the start bit and data bit read 26 us which is ok as per 1000000/Baudrate us, but the stop bit is only about 20us, that looks wrong to me, it should also read the 26us. So I try with different baud rate. But have the same problem ( see below table).

4800Buad rate , Stop bit time =160us ( but it should be 208us)

9600Buad rate , Stop bit time =72us ( but it should be 104us)

38400Buad rate , Stop bit time =20us ( but it should be 26us)

115200Buad rate , Stop bit time =7.2us ( but it should be 8.8us)

I asked the support team, and they say your BRGH value is set to 1, try to change it to 0. So I changed BRGH=0 and this problem is solved.

With BRGH = 0, stop bit error removed and stop bit measures 26uS. We still need to test this with other baud rates too.

Q1) Why BRGH making difference in stop bit baud time only? We are using 8 MHz Crystal.

Q2) Data sheet says BRGH=1 for high speed enable, what does it mean here by high speed, is it baud rate, if so which baud rate is considered to high speed?

Q4) When to use BRGH=0 or when to use BRGH=1, as per test it was observe stop bit baud error in every baud rate as per above given test result table.

Link of uC

http://ww1.microchip.com/downloads/en/DeviceDoc/en026583.pdf http://ww1.microchip.com/downloads/en/DeviceDoc/39747F.pdf

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P 146-149 defines why and how

Always refer to the datasheet using Search in this case for BRGH

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  • 1
    \$\begingroup\$ Where exactly does the datasheet discuss the nonstandard length of the stop bit? \$\endgroup\$ – pericynthion Sep 27 '18 at 17:25
  • \$\begingroup\$ Where is specifies accuracy implications for clock, data rate with formula, the result is implied. So follow those instructions. If you wish to debate the effects, that a separate issue. When you run a slow clock, the phase error is less critical and thus a runt stop bit >50% is ok. but That's my theory. \$\endgroup\$ – Sunnyskyguy EE75 Sep 27 '18 at 18:42
  • \$\begingroup\$ But If I were you, I would add odd parity. The reason for less critical low speeds is usually perfect Eye Pattern. so 47us of truncated clk phase margin @ 4800 Bd is negligible then it is less at higher speeds for an end of the stop bit. This register affects the fractional divider ratios, I believe or countdown for stop sub bit timing. This is to accommodate different Clks for same baud rate as per the formula given in datasheet. THese may affect uC uW dissipation slightly. \$\endgroup\$ – Sunnyskyguy EE75 Sep 27 '18 at 18:54
  • \$\begingroup\$ @pericynthion did you understand me? ( who was that idiot (-1) Dave?) \$\endgroup\$ – Sunnyskyguy EE75 Sep 29 '18 at 19:40

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