I have a circuit that is switching a transformer primary winding from 15 volts to ground, through an N-channel MOSFET at 50 kHz. I was seeing occasional field failures and found that every time the MOSFET was switched off, a 90 volt 100 ns flyback voltage spike was created. This circuit had no flyback diode. The Vds of the MOSFET is 80 volts.

I added a 1N4148 flyback diode and the spike shrank to about 50 volts and about 30 ns at half power. I expected more reduction and would like to remove more of the spike. Any ideas of other methods for suppression?

I thought about the zener clamp over the weekend. Many thanks for the input and the easy to read answer. My load in this case is a piezo transducer. The point of all this is to make a 50khz noise. My situation is a little more complicated in that I have two primaries run in opposite directions with two Mosfet switches in one SO8 package. I need to add two zieners to fix this. Its also complicated by the same PCB is asked to run either at 75khz or 50khz software dependent. My diode will have to work for 75khz and that will like also work for 50khz. This morning I discovered that my primary transformer windings are between pins 1 to 3 and 2 to 4 not 1 to 2 and 3 to 4 like I thought. When I put the fly back in correctly I saw exactly what you predicted, my output power was lowered to less then half. Time to hunt down some suitable parts for test. Thanks!

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    \$\begingroup\$ can you post a (simplified)schematic? \$\endgroup\$ – Navaro Sep 28 '18 at 19:12
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    \$\begingroup\$ seriously a puny 1N4148? Diodes have internal resistance Ri~0.5 to 1/Pmax rating, How much did you expect if Ri is ... compute delta V/delta I and computed stored energy that must be shunted vs SOA for Diode or simply use a diode rated for same pulse current. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 28 '18 at 19:16
  • \$\begingroup\$ The transformer primary has one side connected to 15v. The other side is connected to the drain of a Mosfet. The Source is ground. The gate is driven by our processor. I put the 1N4148 across the transformer winding cathode to 15V. anode to the Drain node. Its all very tight SM PCB The circuit is part of an ultrasonic drive circuit. The 50Khz is the resonant frequency of the piezo transducer. It basically makes 50 Khz sound. I didn't design it, I inherited responsibility for it. \$\endgroup\$ – Robert M Gifford Sep 28 '18 at 19:25
  • \$\begingroup\$ Generally spike or over-shoot can be reduced by 3dB at best. Reducing it more causes energy to be wasted as heat in the flyback diode. \$\endgroup\$ – VTNCaGNtdDVNalUy Sep 28 '18 at 20:07
  • \$\begingroup\$ @Sparky256 This is not correct. You are not dealing with signals you would use dB for. \$\endgroup\$ – Jack Creasey Sep 29 '18 at 1:10

From your description your schematic must look something like this:


simulate this circuit – Schematic created using CircuitLab

I've only got a 1:1 transformer in this schematic, you will have in all probability 10:1 or something similar.

I have included (but not connected) the two potential solutions to your problem.

  1. Connect a diode across the transformer primary. This is not a good solution as I will show and may cause both power supply overload and FET failure.

  2. A Zener Diode to clamp the output and put all the stored energy to use in the output.

Let's look at the simulation result for the schematic with neither the Diode or the Zener.

enter image description here

Here, notice the VDD spike similar to what you are seeing is around 100V. Notice also that the output voltage is very asymmetrical with a well formed forward voltage but just a spike for the reverse. This will be modified by the highly capacitive load you have, which I did not include here.

Now let's attach the Diode to V_M1 and look at the result:

enter image description here

Now the energy stored in the transformer inductance is dissipated in the Diode, but since this results in a long diode conduction period, when M1 turns on again it has to finally dissipate the energy left. This results in the current through the transformer in forward mode rising significantly and may result in FET failure.

Lastly let's show the correct way to clamp the inductive spike and get as much of this energy returned as useful drive for your load by connecting the Zener to V_M1:

enter image description here

Here, notice that the M1 VDD excursion is clamped at 33V, about twice the inbound power supply voltage. This does result in an asymmetrical waveform, but with far less distortion and a useful part of the stored energy is returned to the load. You have to make sure that the conduction period of the Zener is less than half of you drive period to ensure that you don't cause an increase in the M1 current. A good rule of thumb here is to limit the excursion to 2* the supply voltage as I've done here.

Adding a Zener will IMO solve your problem of FET failure due to the inductive spike, AND will return as much of that energy to the output as is possible.

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  • \$\begingroup\$ Could you maybe put in dotted lines where to connect the zener? I don't see where it needs to go. \$\endgroup\$ – JRE Sep 29 '18 at 7:08
  • \$\begingroup\$ @JRE The Diode or the Zener connect to V_M1 in the diagram. \$\endgroup\$ – Jack Creasey Sep 29 '18 at 16:27
  • \$\begingroup\$ Your zener on the output configuration neglects leakage inductance, of which there is always some. The OP should probably still have something on the input -- perhaps a diode feeding an RC snubber circuit, or an appropriately-sized zener on the input. \$\endgroup\$ – TimWescott Oct 1 '18 at 23:06
  • \$\begingroup\$ @TimWescott I disagree. Show me a simulation (or even a partial schematic) where leakage inductance generates a spike on the input. \$\endgroup\$ – Jack Creasey Oct 1 '18 at 23:11

Here's an LTSpice screenshot showing why you need a snubber if you're going to switch currents quickly.

Note that the peak voltage on the MOSFET drain is a simulated 1.8kV -- it would never get this high in real life; instead it would fry the FET.

Schematic & simulation results

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