I am trying to understand what is the correct way of doing such application, so please do not ask for complete code because each component is working fine on its own. I am struggling in the way of making them work together. I do not know the correct approach yet.
I have three vhdl modules adc, ft2232 usb and fifo modules.
- ADC module is getting samples over spi. Its sample rate is 500KHz.
- USB module is ft2232h usb implementation where it is achieving around 2 megabytes transfer to pc.
- Fifo module works as well where i can read and write data on it. I used this code below also tried xilinx's ip core both works. Fifo code
I want to buffer adc samples directly to pc. But what confuses me is that fifo cannot serve to both adc's write and usb's read operations simultaneously. Since they are two seperate processes they might try to use fifo at the same time. Should i define a busy flag to wait during read or write operations.
I appreciate any help.