I am trying to understand what is the correct way of doing such application, so please do not ask for complete code because each component is working fine on its own. I am struggling in the way of making them work together. I do not know the correct approach yet.

I have three vhdl modules adc, ft2232 usb and fifo modules.

  1. ADC module is getting samples over spi. Its sample rate is 500KHz.
  2. USB module is ft2232h usb implementation where it is achieving around 2 megabytes transfer to pc.
  3. Fifo module works as well where i can read and write data on it. I used this code below also tried xilinx's ip core both works. Fifo code

I want to buffer adc samples directly to pc. But what confuses me is that fifo cannot serve to both adc's write and usb's read operations simultaneously. Since they are two seperate processes they might try to use fifo at the same time. Should i define a busy flag to wait during read or write operations.

I appreciate any help.

  • \$\begingroup\$ If you are using dual port RAM then it should work, if not then a token mechanism (or time share method) is needed. \$\endgroup\$
    – Andy aka
    Commented Sep 30, 2018 at 16:02
  • \$\begingroup\$ Thanks andy. So i need a flag to indicate if fifo is ready to be used or not. Secondly does xilinx have option to select dual port ram in fifo core config. \$\endgroup\$
    – nandflash1
    Commented Sep 30, 2018 at 16:05
  • \$\begingroup\$ You need to investigate the particular FPGA you intend to use and find out if it has support for dual-port RAM. If it does, read the synthesis manuals to find out how you write VHDL to infer such a RAM. The documentation will tell you what you need to know about control signals. \$\endgroup\$ Commented Sep 30, 2018 at 20:26

2 Answers 2


But what confuses me is that fifo cannot serve to both adc's write and usb's read operations simultaneously.

Sure it can! That's why it has separate write and read ports. They operate completely independently of each other.

  • \$\begingroup\$ Thank you. Are you talking about the fifo design that is coming with xilinx ip ore's fifo generator (for serving different processes at the same time). For example the fifo code that i refered with link is not a design that can serve both read and write simultaneously right. \$\endgroup\$
    – nandflash1
    Commented Oct 1, 2018 at 19:07
  • \$\begingroup\$ Both the Xilinx IP FIFO and the FIFO you linked to are perfectly capable of doing reads and writes simultaneously. Have you seen any indication that they can't? \$\endgroup\$
    – Dave Tweed
    Commented Oct 1, 2018 at 19:25
  • \$\begingroup\$ I get it now. For the code i posted, even if the write enable and read enable both become logic high the process will first do one if loop and then do the second if loop and both read and write will be served in one clock cycle. Since the process's inside is sequential i tought it cannot serve. Now there is no problem then. I can use fifo deisgn to buffer adc to usb without any problem. Thank you again \$\endgroup\$
    – nandflash1
    Commented Oct 1, 2018 at 19:36

Based on our use of Xilinx IP cores I am going to assume you are using a Xilinx FPGA.

Both Xlinx ISE and Vivado have language templates for FIFOs that support reading from one process and writing from another process.

At the hardware level Xilinx FPGAs have 18K/36K bit block RAMs that can be used as FIFOs. The block RAMs have separate read and write ports that can be accessed by different processes (and even different clock domains) at the same time. The Xilinx synthesizers are typically pretty good about inferring the use of block RAMs if you write your FIFO in a way that is similar to the templates in the Synthesis user guides.

In 7-series Xilinx FPGAs you can also use a one LUT-6 primitives to construct small FIFOs up to 64 entries deep. Each LUT-6 can be used as a 64 x 1 bit dual port RAM, so you would used a number of LUT-6 elements equal to the with of your FIFO elements. Again the synthesizer usually infers the LUT-6 based RAM64X1D elements if you code the FIFO according to the Xilinx templates. Similar usage of the LUT-4 elements in older FPGAs should be possible as well.

Most FIFOs have a full/empty flag. You shouldn't need a separate busy flag since concurrent read/write is supported.

  • \$\begingroup\$ Thank you. Sorry for my ignorance but where are those templates. Is it ip core related. \$\endgroup\$
    – nandflash1
    Commented Oct 1, 2018 at 19:09
  • \$\begingroup\$ @nandflash1 If you are using Xilinx Vivado; then the Flow Navigator pane is located on the left side of the window by default. The language templates are located near the top. Click on "Language Templates" and a window will open. The window has templates for Verilog, VHDL, and XDC. \$\endgroup\$
    – user4574
    Commented Oct 2, 2018 at 3:11

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