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I'm trying to run an old Bitcoin miner project in Vivado. The old code is written in Verilog and the rest of my project is in System Verilog.

I have a syntax error I don't know how to solve. It basically boggles down to a single line (that you can see in the full source code here)

data15_p1 <= `S1( S[i-1].data[`IDX(15)] );

Expanding the macro manually and cleaning it up to replicate the error, I get:

data15_pl <= ( { S[i-1].data[511:480][16:7] } );

Here is what I understand is happening: the IDX macro takes a 32 bit subset from the 512 bits s[].data. [16:7] is then used to try and take bits 16 to 7 of those 32, but Vivado complains with the "Range is not allowed in a prefix" error.

Do I need to rewrite the code using a temporary wire variables to get this to work?

Edit: I think not because I can't use a wire in that scope? Using a register would add delays. Maybe the only option is manually expanding and changing all of the defines?

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Changing the file extension from .v to .sv got me past the syntax error and on to synthesis errors that I cannot fix (part select out of range of prefix), as some people in old Xilinx thread, which makes me think I need to rewrite this.

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