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I have read some about computer memory and the article said DRAM is mainly made from a transistor to direct the electricity and a capacitor to store them. I don't understand how it fills certain capacitors and leaves some open to create ones and zeros.

At first I thought it was just a sequence of electrons and spaces lacking electrons, but I don't see how the next series of electrons after a space would know to skip one transistor and go to the next instead of just filling the first transistor.

Then I learned there is a bit line where one means write and zero equals don't write, but how does it know where to write and not write? Why wouldn't the first transistor just process the write or not write over and over?

Ok, I'm going to add an example to this. Lets say I had four transistors and capacitors. How would I make the first one a one, the second a zero, the third a one, and the fourth a zero?

How does this work?

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closed as too broad by Elliot Alderson, Marcus Müller, R Drast, Dmitry Grigoryev, awjlogan Oct 6 '18 at 13:16

Please edit the question to limit it to a specific problem with enough detail to identify an adequate answer. Avoid asking multiple distinct questions at once. See the How to Ask page for help clarifying this question. If this question can be reworded to fit the rules in the help center, please edit the question.

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    \$\begingroup\$ Welcome to EE.SE. You are asking multiple questions. Memory addressing is often called memory mapping, as it is not the same for all types of memories. Also you ask of the details of how Dram works. There is no short answer less than the size of a book. Please narrow down your questions, and what research have you done on your own? Use the search term 'Dram' and you will learn a lot. \$\endgroup\$ – Sparky256 Oct 1 '18 at 23:44
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    \$\begingroup\$ You are aware that RAM has an address bus (to select a range of adresses in memory) and a data bus (to read/write the various bits to that address)? So if you have 4 bits of memory, you could have a 2-bit address bus (giving 4 possible addresses) and a 1-bit data bus (to read/write the single bit at each address), or no address bus (single address) and a 4-bit data bus, or even a 1-bit address bus (2 addresses) with a 2-bit data bus. I'll let others explains how the RAM will select a specific range of bits based on what is present on the address bus and how it reads/writes the data. \$\endgroup\$ – jcaron Oct 1 '18 at 23:44
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You are confusing a description of one memory cell (the single transistor and capacitor in DRAM), and the whole memory circuit. The memory cells are surrounded by circuitry that gets the data out of the cells on a read, and back into the cells on a write -- and with DRAM, it's complicated, because the whole business is optimized to minimize the amount of circuitry per bit. This comes at the expense of complicated read, write, and refresh actions.

You have done the obvious and read the Wikipedia article? The first figure in the section titled "Principles of Operation" shows a few cells and the surrounding circuitry.

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  • \$\begingroup\$ I know the difference between the cell and the circuit. (That isn't meant to sound smart aleck like, I'm just explaining what I have read.) I have been looking at sites like Hackaday and Instructables, where people have made simpler versions of SRAM and DRAM. The illustration and explanation on one of those sites was simplified and didn't show the address line and bit line as being two unique lines. I took the diagrams showing them as unique lines like on Wikipedia to be a teaching tool and the Instructables diagram to be the real way when it was the opposite. \$\endgroup\$ – user197001 Oct 3 '18 at 15:28
  • \$\begingroup\$ There are a lot of different ways to make it work, and actual designs are proprietary. What I'd trust the most would be papers by researchers and students showing actual schematics of what they've actually done. After that would be 4-th year and graduate-level digital circuits books intended for EE students. \$\endgroup\$ – TimWescott Oct 3 '18 at 17:54

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