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Sorry if this has been asked previously, but I couldn't find anything here or elsewhere on Google (but maybe I'm searching the wrong terms).

I'm trying to design a Type 2 compensator for a PWM chip I'm using. There are two main operating states - a no load state, and a loaded state. The circuit starts in the no load state, and transitions to a loaded state some time later (and never goes back). In order to get loop stability in the loaded state, I need to slow my loop response speed down a lot by lowering the DC gain with the compensator. This, however, causes the response time of the no load state to drop drastically. It's still stable, but it's very slow, and I'd like to speed it up.

I thought about implementing two compensator designs, one for the no load state and one for the loaded state. The way I would switch between these two loops is by changing the input resistance to the compensator (so I can shift the entire gain of the compensator up or down). This could easily be done by an analog switch, which would change the input resistance to either R1 or R1||R1a.

schematic

simulate this circuit – Schematic created using CircuitLab

I'm not exactly sure what happens during the transition between the two compensator designs. I can't find any literature about trying this out, though like I said, I might not be searching the right terms. Any insight would be appreciated!

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Gain scheduling is the term you're looking for.

As long as the transition is instantaneous, what's going to happen is that you'll get a glitch on the output that's filtered by C2.

As long as you make the transition at a point when the loop is stable, you'll be going from a stable system to a stable system, and you'll have no problem. Even if you switched after you got into "run" mode, you'd still be switching to a stable system and you'd have no problem.

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  • \$\begingroup\$ Welcome here Tim. I'm sure your contributions will be important to the fascinating topic of Control Systems. \$\endgroup\$ – Dirceu Rodrigues Jr Oct 3 '18 at 16:40
  • \$\begingroup\$ That's exactly what I was looking for, thanks so much! \$\endgroup\$ – Nick U. Oct 3 '18 at 17:43
  • \$\begingroup\$ Modify V1 rise time to match startup feedback rise time due to V1 offset. Then the step function disturbance is eliminated that causes ringing so you do not need to reduce the start gain so much that it is too slow. 10% gain or more may be ok but higher is faster and lower mismatch in Vcm differential DC voltage on startup must be reduced. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Oct 3 '18 at 22:55
  • \$\begingroup\$ @TonyEErocketscientist Unfortunately, V1 is internal to the PWM chip and I don't have access to it. \$\endgroup\$ – Nick U. Oct 4 '18 at 12:11

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