# CMOS Inverter-based question from Sedra&Smith, Microelectronic Circuits

Exercise 4.47 from Microelectronic Circuits, 6th edition, Sedra & Smith.

I am unable to analyze the following question. Can anyone help me solve it? I only know that the circuit won't remain symmetric.

Consider a CMOS inverter with $$\V_{tn} = |V_{tp}| = 2V\$$, $$\(W/L)_{n} = 20, (W/L)_{p} = 40\$$, $$\\mu_{n}C_{ox} = 2\mu_{p}C_{ox} = 20\mu A/V^{2}\$$ and $$\V_{DD} = 10V\$$. For $$\v_{I} = V_{DD}\$$, find the maximum current that the inverter can sink while $$\v_{O}\$$ remains $$\\leq 0.5 V\$$. • where is the circuit?
– Big6
Oct 3, 2018 at 16:34
• I haven't drawn it here since I assumed you would consider it to be the classic PMOS-NMOS circuit. Oct 3, 2018 at 16:37
• And who are Sedra & Smith? If it's a text book you should give us the title and you should probably quote the page number too. Put all the info in the question rather than in the comments. Oct 3, 2018 at 16:39
• Sorry, my bad. I hope the question is clear now. Oct 3, 2018 at 16:48
• I only know that the circuit won't remain symmetric. How do you mean? The circuit is what it is. You probably mean that the current conducted by NMOS and PMOS will not be equal. Your first step should be to look at the circuit and think what would make it sink the maximum current. This tells you something about $V_i$ and what NMOS and PMOS are doing. Which device(s) determine the sink current? Then apply the formula for the NMOS/PMOS in that state to determine the current. Oct 3, 2018 at 17:24

I'll give one approach, let's focus on the NMOS for now since the input of the inverter is VDD, this should be ON whereas the PMOS should be OFF. Assume the NMOS is in the triode region (a switch "fully" on). You have:

$$I_D=\mu_nC_{ox}\frac{W}{L}\bigg[(V_{GS}-V_{tn})V_{DS}-\frac{V_{DS}^2}{2}\bigg]$$

Notice that for small values of $$\V_{DS}\$$, the quadratic term could be negligible.

$$I_D\approx \mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{tn})V_{DS}$$. So the channel resistance, is approximately,

$$R_{DS_{on}}\approx\dfrac{V_{DS}}{I_D}=\dfrac{1}{\mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{tn})}$$

With that, you can estimate how much current you can pass through the NMOS and not exceed the $$\V_o\$$ requirement < 0.5V since:

$$V_o\approx I_D\cdot R_{DS_{on}}\tag1$$

You have all the values for the constants to find the channel resistance. You have $$\V_o\$$, so you only have to solve for $$\I_D\$$ in (1).

How small needs $$\\dfrac{V_{DS}^2}{2}\$$ to be compared to $$\(V_{GS}-V_{tn})V_{DS}\$$ for the approximation to be accurate? $$(V_{GS}-V_{tn})V_{DS}>>\dfrac{V_{DS}^2}{2}$$ $$(V_{GS}-V_{tn})>>\dfrac{V_{DS}}{2}$$

$$V_{DS}<<2\cdot(V_{GS}-V_{tn})$$

In this problem, you are looking for a $$\0.5\text{V}\$$ max at $$\V_{DS}\$$. That could be considered a lot smaller than $$\2(10-2)=16\text{V}\$$.

This maximum voltage requirement on the output net, just wants to ensure that Vo is low enough to be considered a '0' logic when you have '1' at the input of the inverter.

Notice that if the input voltage were 0V instead of VDD, you'd need to do follow a similar procedure for the PMOS device. In such case, you'd be looking at minimizing the drop across the PMOS on-resistance so that the output voltage is still high enough to be read as a '1'.