I'm doing a timing analysis on the SPI bus connected to an EEPROM (25AA128T-I/ST) on a product and parameter 11 (Clock Delay Time) seems to be less than self explanatory as to what it is for.
My assumption is that it is for a multi-slave bus and that the CS line has to be released for at least 50nS before the bus can be used for another device. However, the way it is drawn it looks like the clock is still finishing a transfer to this first device.
If it is still finishing its transfer when the CS line goes high, that violates how my understanding of how a SPI bus works. Which is that is the entire communication should be encompassed by an asserted CS line.
Is this just a bad drawing or does my understanding of the SPI bus need to be tweaked?