I'm working on a flash chip "W25Q128BV". I get really confused on the operating frequency of this chip. 3 differnet Clock frequencies about the chip

Timing of the instruction Read Data(03h) As we can see, "Read Data" instruction is comprised of 3 steps for master: sending opcode, sending address, and reading data from flash. My question is that can I use 104MHz for sending opcode or address? I think master must use clock frequency below 33MHz for reading data.

And I have the same question for Quad SPI and Dual I/O instructions. The datasheet says the max frequency for them is 70MHz. Taking instruction "Fast Read Quad Output(6bh)" for example, enter image description here this instruction is comprised of 4 parts: sending opcode, sending address, sending dummy clocks, reading data. What is the max frequency of dummy clocks, 70MHz or 104MHz? What is the max frequency for sending opcode and address, 70MHz or 104MHz?

I have spent lots of time for this question on Google, but I couldn't find similiar questions and answers. I found that most people use a low frequency to control spi flash such as 30MHz. So they don't need to worry about the max frequency of a particular instruction. For some purpose, I have to operate this flash chip as fast as possible.

What's more, I also read some datasheets of similiar flash chips, such as N25Q128A and S25FL128. All of these flash chips use lower max frequency for instruction "Normal Read", but the datasheets don't tell the specific frequency request for different parts of instruction "Normal Read".


2 Answers 2


Unless the datasheet states otherwise, you should assume that the clock speed should remain consistent throughout a single command. (For instance, for a single-SPI Read Data instruction, the entire instruction should be clocked at 33 MHz; you shouldn't try to clock the instruction or address at 104 MHz.)

In any case, most microcontrollers won't even allow you to change the SPI clock speed partway through a transaction, so this is kind of a moot point. :)

  • \$\begingroup\$ I agree. I think the datasheet's wording is poor, and they are using the term "instruction" to refer both to the whole transfer, and the first byte of the transfer. \$\endgroup\$
    – Annie
    Oct 4, 2018 at 3:17
  • 1
    \$\begingroup\$ Actually, to be technical, SPI is synchronous so you are allowed to vary the clock frequency, so long as you do not exceed the maximum frequency (there may actually be a minimum frequency, check the datasheet). This is useful for software bit-banging which generally produces a very jittery clock. \$\endgroup\$
    – DoxyLover
    Oct 4, 2018 at 3:58
  • \$\begingroup\$ Thanks for your answer. I think it is also difficult to change the clock frequency during one command, which often leads to unstable spi clock. \$\endgroup\$
    – HYF
    Oct 4, 2018 at 4:21

What is the max frequency of dummy clocks, 70MHz or 104MHz?

Depends on the interface used: 70MHz for QSPI (and "Dual I/O"), 104MHz for SPI.

All of these flash chips use lower max frequency for instruction "Normal Read",

They need to, since there is no dead time between the last address bit and the first data bit. That is why the "normal" or "legacy" read opcode required a slower clock rate - in order to allow the chip to process the address correctly.

That also means the "slow clock" would only be required for the address bytes and the first data byte in theroy.

In practise, you should always use the proper "Fast Read" opcode, because properly changing the clock rate on the fly will be much slower than just reading the additional dummy byte.

  • \$\begingroup\$ Thanks for your answer. Since I'm using a FPGA to control the flash chip, I have to carefully choose the frequency. I think the best choice is using 33MHz to send opcode and address for instruction "Read Data". I also reliaze that when reading many bytes from a flash chip, the time spent on sending opcode and address is not very important. \$\endgroup\$
    – HYF
    Oct 4, 2018 at 16:25

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