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What would the logic gate diagram look like for a JK Latch? I know what a JK flip-flop looks like, but how would you build a latch with only J and K inputs, without a clock input?

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This is pretty easy to derive by hand. A JK latch is just like an SR latch except with a 11 input, an SR latch does nothing while a JK latch toggles. So, basically you can right out the truth table and solve it with a Karnaugh map.

The lack of a clock makes toggling pretty useless here; I've never seen a JK latch in the wild but they are theoretically quite possible.

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    \$\begingroup\$ I believe you would also have to make sure the transition was defined regardless of which input went high first and that it only toggled once until both inputs had gone low, and this would also cause momentary blips in the signal if it was high and received Reset first or if it was low and received set first. \$\endgroup\$ – K H Oct 4 '18 at 4:31
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From Know all about Latches and Flip Flops:

JK latch is similar to RS latch. This latch consists of 2 inputs J and K as shown in the below figure. The ambiguous state has been eliminated here: when the inputs of Jk latch are high, then output toggles. The output feedback to inputs is the only difference we see here, which is not there in the RS latch.

JK latch

Compared to the JK flip-flop:

JK flip-flop

So, you just remove the AND input for the clock.

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  • \$\begingroup\$ This doesn't seem to work on logisim. There's an error around the NOR gates. \$\endgroup\$ – Ohbhatt Jan 8 at 6:54

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