What would the logic gate diagram look like for a JK Latch? I know what a JK flip-flop looks like, but how would you build a latch with only J and K inputs, without a clock input?
This is pretty easy to derive by hand. A JK latch is just like an SR latch except with a 11 input, an SR latch does nothing, while a JK latch toggles. So, basically, you can write out the truth table and solve it with a Karnaugh map.
The lack of a clock makes toggling pretty useless here; I have never seen a JK latch in the wild but they are theoretically quite possible.
JK latch is similar to RS latch. This latch consists of 2 inputs J and K as shown in the below figure. The ambiguous state has been eliminated here: when the inputs of Jk latch are high, then output toggles. The output feedback to inputs is the only difference we see here, which is not there in the RS latch.
Compared to the JK flip-flop:
So, you just remove the AND input for the clock.