Currently, I am using an ADC with an external trigger with the caveat that the edge of the trigger must be within +/- 25ns of the ADC's clock (See Figure 3 of the datasheet). The ADC's clock is available on a pin of the ADC.
In this case, the GPIO used to operate the trigger is not synchronized with the ADC clock and therefore synchronization is necessary. Apparently, the best way to do this is with two cascading D flip-flops connected to the same clock in order to ensure that there is no race condition between the setup time and the clock pulse.
There appear to be some gotchas with this approach. Some sources recommend a delay between the two flip flops for added safety. Others say that "synchronization hardened" FFs are necessary.
So, what's the best way to solve this problem? Is there a ready-made logic family that will do the trick? Or a specific IC?