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Consider the following circuit with two OR gates:

schematic

simulate this circuit – Schematic created using CircuitLab

and the Time Simulation: enter image description here The OR gates with both inputs 0 generate 0, and after one input is set to 1, they remain with 1 as long as there is current. The circuit has memory.

Now consider the implementation of OR with diodes (let's call them diode-ORs):

schematic

simulate this circuit

and the Time Simulation: enter image description here In this case, the diode-ORs always generate a 0 whenever both inputs are 0. The circuit has no memory. And there is a loss of voltage, that would accumulate if more diode-OR gates were cascaded.

My question is the following: is there another implementation that behaves like diode-ORs (i.e., without memory even in the presence of feedback loops) but does not have a cumulative voltage loss (or has only a very small voltage loss)?

Or put another way: can we replace each of the two diode-ORs by a circuit so that the whole system behaves the same way, except that there is no cumulative voltage loss (or the voltage loss is very small)?

Maybe using pass transistor logic? (https://www.electronics-tutorial.net/Digital-CMOS-Design/Pass-Transistor-Logic/OR-gate-using-pass-transistor-logic/)

Dave Tweed suggested to use a "better diode" and that is a correct answer to the question. Is there any other alternative? A problem with that solution is that it cannot be used for the AND case, which I would also like to handle in that way (with low voltage drop, and without memory even in the presence of fededback loops) because diode-ANDs have memory when there is positive feedback (https://en.wikipedia.org/wiki/Diode_logic#/media/File:Diode_AND2_Ideal_Diode.jpg).

I am a computer scientist and I am interested in the answer mainly for theoretical reasons and for teaching purposes. I know that the feedback loop is not needed to generate the outputs of the circuit.

Thank you!

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  • \$\begingroup\$ The positive feedback loop is the memory. Refer to AoE chapter on Comparators and Hysteresis. Also consider that the OR gate has high-impedance inputs, whereas the diode does not. Use a proper source resistance model instead of ideal voltage sources and you will see how your question is flawed. The ideal voltage source masks the fact that the diode-OR steals power from its input, while OR gates do not. This is why OR gates are capable of supporting a positive feedback loop, creating a memory cell. The memory is not inherent in the gate implementation as you seem to suggest. \$\endgroup\$ – MarkU Oct 4 '18 at 22:19
  • \$\begingroup\$ Thanks MarkU. I will check the reference. I get what you say, but I don't understand why the question is flawed. A possible answer would be: "yes, just try with a diode which has an infimal voltage loss". I know there are no such diodes, but the fact that this answer would be valid if such a diode existed shows that the question is not flawed (although I can understand that from your perspective it may look as irrelevant or uninteresting). \$\endgroup\$ – Javier Oct 4 '18 at 22:32
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My question is the following: is there another OR implementation that behaves like diode-ORs (i.e., without memory even in the presence of feedback loops) but does not have a cumulative voltage loss?

This is logically impossible.

The expected behavior of an OR gate is:

  • When either input is held HIGH for a sufficient amount of time, the output will be brought HIGH and remain HIGH until after both inputs cease to be HIGH.
  • When both inputs are held LOW for a sufficient amount of time, the output will be brought LOW and remain LOW until after at least one input ceases to be LOW.

An OR gate is also required to produce a relatively strong signal (for example, a HIGH output must be greater than 4 V and a LOW output must be less than 1 V) and to accept a relatively weak signal (for example, any input greater than 3 V must be recognized as HIGH and any input less than 2 V must be recognized as LOW)

So, suppose that we have an OR gate (any OR gate) whose inputs are A and B, and whose output is C. Suppose, also, that C is connected to B. We then bring A HIGH for a while, causing C to be brought HIGH as well. Then:

  • C must remain HIGH until after A and B have both ceased to be HIGH (by the definition of an OR gate).
  • B will remain HIGH as long as C remains HIGH, because they're connected to each other.

From the above, we can see that the output of this OR gate will remain HIGH forevermore.

In response to your comment:

Maybe I have used the name OR gate incorrectly, but then just delete the word OR from the question and then there is no logical inconsistency any more: is there another implementation that behaves like diode-ORs (i.e., without memory even in the presence of feedback loops) but does not have a cumulative voltage loss?

Sure, absolutely. Take an OR gate and then alter it by adding a timer which forces its output LOW once every ten seconds. Then this resulting OR-like device does not have memory in the presence of feedback loops, and it doesn't have a cumulative voltage loss, either. But I don't know whether or not this implementation meets your expectations.

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  • \$\begingroup\$ Thanks for the complete answer! Maybe I have used the name OR gate incorrectly, but then just delete the word OR from the question and then there is no logical inconsistency any more: is there another implementation that behaves like diode-ORs (i.e., without memory even in the presence of feedback loops) but does not have a cumulative voltage loss? \$\endgroup\$ – Javier Oct 4 '18 at 23:40
  • \$\begingroup\$ @Javier I've edited my answer to suggest an implementation. Does the implementation I suggested meet your expectations? \$\endgroup\$ – Tanner Swett Oct 5 '18 at 0:14
  • \$\begingroup\$ Thanks again, Tanner. Unfortunately not, because that is not the behavior of the diode-OR. The diode-OR does not have its output LOW every ten seconds. Put another way: the Time Simulation picture for that implementation would be different than the second one above for the diode-OR. \$\endgroup\$ – Javier Oct 5 '18 at 0:20
  • \$\begingroup\$ @Javier What, specifically, is not satisfactory about my suggested solution? You say it's not satisfactory "because that is not the behavior of the diode-OR", implying that in order to be satisfactory, a solution must behave like the diode-OR. But you also say that you want something that does not have a cumulative voltage loss, implying that in order to be satisfactory, a solution must not behave like the diode-OR. It's impossible to satisfy both requirements at once, so I must be misunderstanding one requirement or the other. \$\endgroup\$ – Tanner Swett Oct 5 '18 at 0:50
  • \$\begingroup\$ Sorry Tanner, I should have written as in the post: the solution should behave like diode-ORs (i.e., without memory even in the presence of feedback loops) but does not have a cumulative voltage loss. Or at least that loss should be as small as possible. In your solution there is no cumulative loss, but the rest does not remain the same, or similar. (Anyway, thanks for trying to help, I see this is not been easy for all you, and I appreciate you are making this effort). \$\endgroup\$ – Javier Oct 5 '18 at 13:57
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Consider your diode circuit: when the inputs are both zero volts, where would the energy come from to maintain an output at anything other than zero volts?

The "real" or "traditional" OR gates have an implicit supply voltage that will maintain the state of the outputs. Simulation tools sometimes "handwave" this away so as to not clutter up the schematic with unnecessary supply connections.

Consider the following circuit diagram representing a traditional CMOS OR gate implemented with transistors: enter image description here

In this circuit, the circuit elements that comprise the OR gate are powered from VDD, and thus can provide power to the output Q. In your diode circuit, there is no such power supply, and thus no latching, or as you put it, memory.

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  • \$\begingroup\$ Thanks for the explanation, Brendan, but I do not get what is your answer to the question (maybe I am missing something...) \$\endgroup\$ – Javier Oct 4 '18 at 21:11
  • \$\begingroup\$ Javier, traditional OR gates do not transfer energy directly from the inputs to the output, instead that energy comes from a separate power supply rail. In a Diode-OR, energy must come from the input to power the output. When your input goes to zero volts, so must the output. \$\endgroup\$ – Brendan Simpson Oct 5 '18 at 12:17
  • \$\begingroup\$ Thanks, Brendan. I understand that. I want to have exactly the behavior you described of the Diode-OR, but without that much voltage loss: is that possible? I thought maybe some pass transistor logic (electronics-tutorial.net/Digital-CMOS-Design/…) could do that, given that in this case there is no sepparate power supply. \$\endgroup\$ – Javier Oct 5 '18 at 15:29
  • \$\begingroup\$ There are potentially a million answers to your question. Can you use a diode without a voltage drop? No. You could use a Schottky diode and reduce the diode drop maybe. Depending on what you are driving downstream, perhaps resistors in series with your inputs could work. Or a traditional OR gate. If you don’t want a latching behavior, I’m not really sure why you introduced the cross coupled circuit in the first place. \$\endgroup\$ – Brendan Simpson Oct 6 '18 at 0:06
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There isn't really any feedback in your second circuit. D3 and D4 are simply cross-connected between the two outputs. When both inputs are high, both outputs are one diode drop below the input voltage, but if either input is low, the corresponding output is two diode drops below the other input. If both inputs are low, both outputs are low, because there's no other voltage source.

The problem with the diode circuit is that it is completely passive. It has no gain, and therefore no positive feedback. The circuit with real gates has gain, and therefore the positive feedback that creates memory.

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  • \$\begingroup\$ Thanks Dave. Actually, for me the diode circuit has no problem (except for the voltage loss). I know this is the opposite to the way logic gates operate, but I do want the circuit to have no positive feedback. My question is: is there other implementation of OR gates that behaves like the diode one (i.e., without positive feedback) but has no voltage loss? Maybe with pass transistor logic? \$\endgroup\$ – Javier Oct 4 '18 at 21:38
  • \$\begingroup\$ Yes. A single OR gate behaves in exactly the way you desire. \$\endgroup\$ – Dave Tweed Oct 4 '18 at 21:43
  • \$\begingroup\$ I know that, but that does not answer the question. I do not want to arrange the OR gates differently. I want to implement them differently. \$\endgroup\$ – Javier Oct 4 '18 at 21:48
  • \$\begingroup\$ Your requirements cannot be met. This arrangement automatically has a positive feedback loop which is all you need to create a memory cell with with SET or RESET inputs. So if you want define your logic table needed, someone can help you. If you just want to amplify the diode output or to Vcc use a comparator \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Oct 4 '18 at 22:31
  • \$\begingroup\$ @TonyEErocketscientist: Thanks! I get that is what happens with the usual OR gates. However, this is not the case with diode-OR (as I call them): with them the positive feedback loop does not create a memory. All I want to know is if it is possible to replace each diode-OR by another circuit that has no voltage loss but has a similar behavior (i.e., the positive feedback loops do not create memory cells). This may sound strange to you, but I do research in non classical logics, and somehow there is a connection to this specific question \$\endgroup\$ – Javier Oct 4 '18 at 23:00
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A logic gate amplifies the input signal. If you feed back the non-inverted output signal into the input, the output overrides a weak input signal and thus, the circuit has a memory.

Consider a similar schematic, only consisting of an amplifier with positive feedback. The resistor is placed so you don't "short circuit" input and output. In a logic gate, these are internal parts that separate the multiple inputs

schematic

simulate this circuit – Schematic created using CircuitLab

This circuit has memory. If you connect the input to +V, the output goes to +V, and through the feedback loop, it stays at +V if you let the input float again. And the same for -V. (The switch voltage is set by the amplifier - input connected to GND.)

So, the answer to your question is simple.

  • You cannot have amplification, positive feedback and no memory at the same time.

Because that's a by-product of amplification.

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  • \$\begingroup\$ Thanks for the answer! I get your point. And what about the option without amplification, but with positive feedback and no memory? That is what I am aiming for in the question. I think you can say the diode-OR (with all its problems) does exactly that: no amplification, and no memory even with positive feedback. If we agree on this, then all I am asking for is a circuit that behaves like that diode-OR but has no voltage low. Is this possible? \$\endgroup\$ – Javier Oct 4 '18 at 23:58
  • \$\begingroup\$ How do you achieve that? All non-linearity in nature comes with an entropy side effect. If you want to go without any voltage loss, you certainly need amplification. \$\endgroup\$ – Janka Oct 5 '18 at 0:10
  • \$\begingroup\$ If you are only after a practical implementation, simply place the amplifying stage outside of the feedback loop. Such "gates" aren't cascadeable, though. \$\endgroup\$ – Janka Oct 5 '18 at 0:19
  • \$\begingroup\$ That's a good point, Janka! Then let's say that I want to minimize the voltage loss, while having no memory even with positive feedback. Sorry for not being precise formulating the question. I am interested in this more from a theoretical perspective. It may be interesting for some research I do in non classical logics. \$\endgroup\$ – Javier Oct 5 '18 at 0:29
  • \$\begingroup\$ You have to go linear. An OR gate can be represented as a sum, too. This is achieveable with resistors, as it's just Kirchhoff's node law you employ. Then minimize the currents and you have almost no voltage loss. Or, drop the voltages at all and use current sources and currents for the logic. This all means your energy losses are taken from the logic mesh into your sources and output amplifiers. \$\endgroup\$ – Janka Oct 5 '18 at 0:43

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