Consider the following circuit with two OR gates:
Now consider the implementation of OR with diodes (let's call them diode-ORs):
and the Time Simulation: In this case, the diode-ORs always generate a 0 whenever both inputs are 0. The circuit has no memory. And there is a loss of voltage, that would accumulate if more diode-OR gates were cascaded.
My question is the following: is there another implementation that behaves like diode-ORs (i.e., without memory even in the presence of feedback loops) but does not have a cumulative voltage loss (or has only a very small voltage loss)?
Or put another way: can we replace each of the two diode-ORs by a circuit so that the whole system behaves the same way, except that there is no cumulative voltage loss (or the voltage loss is very small)?
Maybe using pass transistor logic? (https://www.electronics-tutorial.net/Digital-CMOS-Design/Pass-Transistor-Logic/OR-gate-using-pass-transistor-logic/)
Dave Tweed suggested to use a "better diode" and that is a correct answer to the question. Is there any other alternative? A problem with that solution is that it cannot be used for the AND case, which I would also like to handle in that way (with low voltage drop, and without memory even in the presence of fededback loops) because diode-ANDs have memory when there is positive feedback (https://en.wikipedia.org/wiki/Diode_logic#/media/File:Diode_AND2_Ideal_Diode.jpg).
I am a computer scientist and I am interested in the answer mainly for theoretical reasons and for teaching purposes. I know that the feedback loop is not needed to generate the outputs of the circuit.