My current project is using via-in-pad technology for BGA chips. They are proper VIPs: filled with conductive material and planed flat. I would also like to use these VIPs for my discrete decoupling components.
For example, the following components are 0201's (0603 metric), the trace width is 5 mils (0.127 mm), and the green pads are ground. If you look closely, there are 12-mil (0.305 mm) VIPs embedded in the green pads. These VIPs are full-length plated-through-holes, but only connected to a ground plane on the next layer.
(My decoupling traces are actually very short; I'm showing this non-decoupling component to make the example simple)
These boards are double-sided, and so will go through two reflow cycles. They will use lead-free solder.
I am concerned that having a ground-plane connection opposite a surface trace will cause tombstoning during reflow.
- Is this a valid concern?
- If so, can I minimize the issue by providing thermal reliefs on the internal ground layer?
- And, if #2 is true, is this a bad idea anyway? I'd rather not add inductance to my decoupling circuitry...
How is this generally handled?