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I am now working on a verilog testbench file and I want to get a random value in my code, but I have found that Questa Sim uses the same seed again and again. I have read through $random in Verilog doesn't seem to be working and tried typing -sv_seed random in the transcript window, but the program doesn't understand my command. Can anyone give me some hints?

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  • \$\begingroup\$ Reminds me Apple II’s faulty RAND function so we used time of day for a seed \$\endgroup\$ Commented Oct 5, 2018 at 4:00
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    \$\begingroup\$ Just to be sure that you are doing nothing wrong, can you show us some code? \$\endgroup\$
    – Oldfart
    Commented Oct 5, 2018 at 4:07
  • \$\begingroup\$ I have one line: #0 random_out_delay = $urandom_range(31,0); but the problem is that I don't know where to input the "-sv_seed random" command \$\endgroup\$
    – eric yau
    Commented Oct 5, 2018 at 4:33

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The -sv_seed random is an option the to vsim command line. By the time you get to vsim's transcript window, it's too late to change the seed.

When invoking Questa from the shell command

vsim -sv_seed random ...

When starting Questa simulation using the GUI, look for form to fill in vsim options.

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  • \$\begingroup\$ Thanks for your help. If it's too late, what should I do if I want to change the seed before simulation? Where should I type the command "sv_seed random"? \$\endgroup\$
    – eric yau
    Commented Oct 5, 2018 at 5:44
  • \$\begingroup\$ `vsim -sv_seed random <all_other_arguments>. If you are using the Questa GUI, when you go to "Start Simulation" there is an Other Vsim Options form \$\endgroup\$
    – dave_59
    Commented Oct 5, 2018 at 5:52

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