# Implementing a function using decoder, encoder and some gates

Implement the function F(A,B,C,D,E) = A’B’C’DE’+ABCD’E using only the components required from the ones given below:

• One 3:8 decoder with active high outputs and an active high enable input
• One 8:3 Priority Encoder with input no. 7 at highest priority with one active high enable which if disabled forces the outputs to logic low
• One 2 input XOR gate
• One 2 input OR gate
• One 2 input AND gate

My attempts:

• I have noticed that the function has the minterms 2 and 29 - 00010 and 11101.
• I can make the decoder have four inputs using an enable pin (for a variable).
• Drawing the K-Map doesn't seem to simplify anything.
• Applying De-Morgan's law doesn't seem to simplify things.
• Tried using B,C and E in the decoder and A or D in the enable. This provides me with 8 minterms of B,C and E.

I am stuck on how to implement it using only these.

How do I approach this question(and other such design questions) further?

• Welcome to EE.SE! This appears to be a homework question. Note that homework questions on EE.SE enjoy/suffer a special treatment. We don't provide complete answers, we only provide hints or Socratic questions, and only when you have demonstrated sufficient effort of your own. Otherwise, we would be doing you a disservice, and getting swamped by homework questions at the same time. See also here. Oct 5, 2018 at 14:18

There is no set procedure for solving these kinds of problems. It requires a lot of creativity and insight.

Some insights that may prove useful:

• The two patterns are complements of each other.
• Priority encoders are particularly good at detecting combinations of zeros.
• Decoders are particularly good at detecting combinations of ones.

There is a solution that uses exactly the gates listed. (It does not require a "valid" output on the encoder, although that is a normal feature of such a chip.) I'll post it in a day or two if you're still stuck.

The truth table for a priority encoder looks like this:

      Inputs         Outputs
E 7 6 5 4 3 2 1 0    V C B A
-----------------    -------
0 x x x x x x x x    0 0 0 0   <--
1 1 x x x x x x x    1 1 1 1
1 0 1 x x x x x x    1 1 1 0
1 0 0 1 x x x x x    1 1 0 1
1 0 0 0 1 x x x x    1 1 0 0
1 0 0 0 0 1 x x x    1 0 1 1   <--
1 0 0 0 0 0 1 x x    1 0 1 0
1 0 0 0 0 0 0 1 x    1 0 0 1
1 0 0 0 0 0 0 0 1    1 0 0 0
1 0 0 0 0 0 0 0 0    0 0 0 0


The key insight here is that both the first and sixth lines of this table are significant for this problem. Pay attention to the C output. If you wire the inputs correctly, you can make it go low for ABCDE = 000x0 or ABCDE = xxx0x. The remaining question is, how can you use the XOR gate to distinguish between these two cases?

Full solution simulate this circuit – Schematic created using CircuitLab

• Thanks Dave. I am not able to visualize how the encoder with the XOR gate would give me A'B'C'DE'. If you know of any resources that could help me to understand the output of the priority encoder as you want me to see it, it would be of great help. Oct 5, 2018 at 15:53
• Does my edit above help? Oct 5, 2018 at 16:12
• I can insert A,B,C,E into Inputs 7,6,5,4 respectively and 3 would be connected to 1. D would be connected to Enable. XOR can be connected to Outputs B and C to distinguish between the two. A'B'C'DE' is thus implemented. Oct 5, 2018 at 17:26
• Close, but no. You can't use output B because rows 2-5 of the table are also activated for various invalid combinations of inputs. But if you XOR the C output with the D signal, you get what you want. I've put my complete solution into my answer. Oct 5, 2018 at 18:13
• Thanks a lot Dave. I now understand the thought process behind such questions. Oct 5, 2018 at 19:19

The fact that your problem is expressed as a Sum Of two Products gives you a big pointer towards the solution, as you have two complex components and an OR gate available. So it should just be a matter of getting one component to generate one of the products, the other component to generate the other product, and then using the OR gate to combine the two to get the output. You also have two apparently randomly chosen gates to help you out.

The term ABCD’E is the easy one. You have four inputs that need to be 1 and one that needs to be 0. Combine two of the inputs that need to be 1 using the AND gate and you're down to three inputs that need to be 1 and one that needs to be 0, and that can be achieved very easily using your 3:8 decoder.

The second is harder so I'll leave you to try and figure it out, but write out the truth table and study it to see how you can combine the 8:3 encoder with the XOR gate to get the second product.

• Thanks. I could implement ABCD'E easily after that insight. I tried to implement the other term. I can see that I can get four of the terms from the encoder(using enable(used D in enable) and I'll have to directly enter one term into the XOR gate. I saw the expression for the output of Priority encoders and tried to plug in A'B'C'DE' in the expression for the LSB. By hit and trial, I could make the output from the encoder as : A'B'C'D by selecting the appropriate inputs. If I combine E with this using a XOR. I get an extra term in the desired result. Any hints on what I could do now? Oct 5, 2018 at 12:43
• No, you need to get a single term from the encoder/XOR combination. I'll give you a clue - ignore the encoded output bits and concentrate on the Valid output. D is certainly the correct one to use for the enable. Oct 5, 2018 at 12:47
• Q0(The LSB) = (m6'(m4'm2'm1+m4'm3+m5)+m7). [without considering enable] I put m6 = A, m4 = B, m2 = C, m1 = 1 and rest as zero. This gives me A'B'C'. With the enable as D. The expression is A'B'C'D. Getting A'B'C'DE' with a XOR is the challenge for me. I could do it with an AND. Oct 5, 2018 at 14:43
• Like I said, ignore Q0, Q1 and Q2. You're really looking to treat the encoder as a four input OR gate with enable. Oct 5, 2018 at 14:46
• I just can't wrap my head around this one. I am new to this. Oct 5, 2018 at 15:33