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I'm designing a board that contains an MCU and an 8 MHz crystal. I was planning on keeping the MCU power/ground localized and isolated from the main power supply power/ground except at a single point. I understand that for this scheme to work, the MCU decoupling capacitor must provide a low impedance path for high-frequency currents drawn from the MCU.

Does anyone know of any rules of thumb for acceptable frequency response for a capacitor used for this purpose? I'm using a 1uF ceramic through-hole (should probably use surface mount but I've got these things lying around) with the following frequency response:

enter image description here

I'm a little worried that it becomes inductive at only 2.5 MHz. Will this capacitor serve its intended purpose of decoupling an MCU run from an 8 MHz crystal?

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    \$\begingroup\$ A decoupling cap on the MCU supply rather fills the purpose of keeping the incoming voltage to the MCU clean. I'm not sure why you think there will be 8MHz noise coming up in the other direction from there, it would mean some fishy internal layout of the MCU. Maybe you could include a picture of your PCB layout? At any rate, 1uF is too large for high frequency noise. What you should focus on instead to lower noise, is probably to ensure that the crystal layout + any pins used for internal PLL/FLL is good and placed as close to the MCU as possible. \$\endgroup\$ – Lundin Oct 5 '18 at 8:45
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I agree with Lundin's comment that 1 uF is a bit of a high value, especially if you only use a 1uF capacitor.

But to answer your actual question: yes, it will probably just work if your circuit's design isn't sensitive to noise and disturbances on the supply voltage. For example: a LED flasher or a motor driver will probably just work. If you're using this MCU in a design for a GPS receiver then this single 1 uF bypass cap. might not be enough.

What is more commonly done is to use a single 100 nF capacitor, that will take better care of the high frequency signals.

Even better in a sensitive environment (like a radio receiver) is to use multiple capacitors. For example a 100 pF and a 100 nF capacitor in parallel. The 100 pF should be placed as close to the MCU's supply pins as possible and connect to the ground (plane) directly. The 100 pF will then take care of high frequency signals on the supply. Ten also add a 100 nF capacitor which can be a bit further away from the MCU.

Ideally each chip would have it's own decoupling capacitors and if a chip has multiple supply pins it might be good to give each pins it's own decoupling capacitors if the pins aren't close together.

But if your device has no noise sensitive parts you could get away with only having a 100 nF single capacitor.

Pro Tip: if you make a PCB, just add the footprint for the caps, it does not mean they need to be there in the final product. That way if there are issues you can easily experiment with adding extra caps.

Also see EEVBlog's videos on bypass capacitors

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  • \$\begingroup\$ The ground plane and supply plane can act as a very low capacity very high quality capacitor as well which might be useful for some designs (i.e. try to get a large area close to the supply pin), but usually only for very critical designs. I have seen that mentioned on some ultra high efficiency SMPS designs (from LT if memory holds) \$\endgroup\$ – Arsenal Oct 5 '18 at 11:18

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