Biasing Class AB power amplifier with MOSFETs

Question

I am having trouble getting the resistor biasing to meet a minimum 1.25W at the output:

Note, the distortion and watt meter. I was told the SPICE parameters for the FETs didn't really matter. (Although, I would like to know want to populate some values.)

Anyway, here are my calculations...probably riddled with misconceptions:

\$(P_L = 0.5V_P^2/R_L) → V_P = \sqrt{2R_LP_L}\$

\$\sqrt{2*10*2} = 6.324 V\$ // I picked an output power of 2W.

\$V_{DD} = V_P/0.8 = 7.9 V\$

From the TC6215 complementary pair MOSFET datasheet, N-Channel Output Characteristics:

\$2.5 = K_N(5 - V_{GS(th)})^2\$

\$1.5 = K_N(4 - V_{GS(th)})^2\$

Solving for the two equations:

\$K_N = 7.78 A/V^2\$

and \$ V_{GS(th)} = 4.44 V\$ (Edited because 0.534 V is not the right one.)

_________________________________________________________

From SPICE diode because I couldn't find it on the diode datasheet: \$I_s = 2.55*10^{-9}\$

Then, the combined diode voltage:

\$ V_{BB} = (amtOfDiodes)*V_T*ln(I_{Bias}/I_{s})\$

\$ V_{BB} = ? = (3)*0.026*ln(I_{Bias}/2.55*10^{-9})\$

How do I find V_BB to solve for the bias current, to solve for the bias resistors?

I don't know what to put for \$V_{BB}\$ in this schematic:

→ \$ I_{Bias} = 4.77mA\$ (INCORRECT)

_________________________________________________________

KVL loop from top left down to load:

\$ V_{DD} = RI_{Bias} + V_{GS} + Vo\$

\$ 7.9 = R*4.77m + 0.564 + 4.47\$

→ R = 600 Ω (NOT RIGHT)

Only design specifications

• \$P_L\$ > 1.25 W (Major problem.)
• Efficiency > 60%
• THD < 1.5%
• \$R_L\$ = 10 Ω
• 3dB lower frequency < 500 Hz
• Supply voltages ±15 V (maximum)

---

---

Minor Question

Should an input buffer stage be added to minimize distortion:

The voltage drop across resistor R2 provides the bias to Mn and Mp so that crossover distortion is minimized.

Microelectronics 4e Neamen

---

EDIT1

I never did figure out how to calculate V_BB (technically V_GG).

---

Related

Class AB amplifier Design

Answer 1

I never did figure out how to calculate V_BB (technically V_GG).

In theory, the calculations will look something like this:

First, we need to know the MOSFET parameters.

I assumed these parameters:

\$V_{GS(th)} = 3V , K_P = 4 \$ for both transistors.

Nex I pick output stage quiescent current.

I pick this value \$I_Q = 0.1 \cdot \sqrt{\frac{1.5W}{10\Omega}} \approx 40 \textrm{mA}\$

I solve for \$V_{GS}\$

From this:

$$I_D = \frac{K_P}{2}(V_{GS} - V_{GS(th)})^2$$

I get this:

$$V_{GS} = V_{GS(th)}+\sqrt{\frac{I_D}{0.5 \cdot K_P}} = 3V +\sqrt{\frac{40 \textrm{mA}}{0.5 \cdot 4}} \approx 3.14V$$

So, the situation looks like this:

^{simulate this circuit – Schematic created using CircuitLab}

Notice how I connect the \$Q_2\$ source terminal. In your second diagram, you made a mistake in \$X_2\$.

Your P-channel MOSFET is connected backward.

As you can see our bias voltage is quite large (\$V_{BB} = 6.28V\$). And you will need \$\frac{6.28V}{0.6V} = 11\$ eleven diodes to accomplish the job.
This is why it will be better to use a Vbe multiplier (rubber diode) instead.

^{simulate this circuit}

And do not try to build this circuit in real life.

Answer 2

You've gone very badly astray.

At a start, there is your derivation of VGS(th)

and VGS(th)=0.564V

If you look earlier in the datasheet than the point you've linked, you'll see that VGS(th) can vary between 1 and 2 volts (polarity depends on model). So you need a voltage in the range of 2 to 4 volts, and the exact value will depend on the specific unit. 3 diodes in series will give you something on the order of 2 volts, so there is an excellent chance that your bias circuit simply won't do its job since the FETs are running starved for current. Your second circuit shows the proper application for this technique, and it works because pretty much all silicon junctions (non-Schottky, of course) have the same approximate voltage drop and the same temperature coefficient. Note (and this may have been missed) that the circuit is used in power amplifiers with special care taken to thermally couple the transistors and diodes to take advantage of the temperature coefficient matching. If you don't do that, distortion depends on power levels.

Go back to your simulation and check the quiescent current level at the junction of the two FET sources. Is it anywhere near 1 mA? That, after all, is the current level specified for VGS(th).

And before you run off and try to calculate a current value that will produce a voltage drop of, let's say, 3 volts, stop and think. Don't do it.

I suggest trying 4 diodes rather than 3, and check the quiescent current. Then go to 5 if that doesn't work. And maybe even 6, if your Spice model is particularly ornery. Be aware that this incremental approach may well produce a jump in current which produces current levels higher than you like. Sorry to tell you this, but that's tough. You'll have to live with it. In theory, you can start with a large number of diodes, then drop the bias current to a level where the voltage drop is appropriate. This will run the diodes at rather low current, but you can give it a try.

As for your question

I don't know what to put for V? or VBB in this schematic:

you should ask yourself: at what current level(s) will the voltage across the diodes be the same as the voltage drop across the two emitters? Assuming Is is the same for all 4 junctions, does a ratio suggest itself?

EDIT - Simulate the following circuit

^{simulate this circuit – Schematic created using CircuitLab}

Make V1 10 V Pk-pk. You only need to simulate 1 cycle. Find the input values V1 and V2, where V1 produces VOUT1 of 4 volts (which implies a Q1 drain current of 1 mA) and V2 produces VOUT2 of -4 volts (Q2 drain current of -1 mA). In other words, use the circuit to find VGS(th) of the models you are using.

Use V1 and V2 to determine VBB, although in this circuit this should be called VGG - that is what confused me earlier about which circuit you were referring to.