I have a NodeMCU and two LCD devices and an ADS1115 on one I2C bus. The LCD devices have I2C backpacks. The NodeMCU is on 5V USB power and internally operating at 3.3V. The other devices are on the second shared 5V power. Ground is shared.

The NodeMCU is using a logic level converter on SDA/SCL to talk to the rest of the I2C bus.

I have 10K Ohm resistors on SCL / SDA to pull up to VCC (the non-USB 5V supply).

Now I have set up a 2N2222 NPN transistor to interrupt or bridge the ground line of one of the LCD screens (LCD1). That turns on or off the LCD and that works.

What I noticed

Now what I noticed is that when I have LCD1 turned OFF using NPN, the backlight of the LCD1 sometimes flickers (once per second).

After some fiddling I found the flicker is related to I2C bus communication between NodeMCU and LCD2 or ADS1115. I just happened to have some I2C bus traffic to LCD2 once per second (to write the time) and some occasional traffic to the ADS1115, once every nine seconds. All those make the backlight of LCD1 flicker when it is turned off using NPN transistor.

I thought maybe this was due to current leaking through NPN transistor, but if I completely disconnect GND line on LCD1 the backlight still flickers. To state this clearly: LCD1 has VCC and SCL and SDA connected but not GND and the backlight is flickering.

So somehow the SCL / SDA cables going into LCD1 function as brief GND lines flickering the LCD backlight. I understand that SCL / SDA communication requires a device to pull the clock line down to GND so I assume at that point it is grounding the 5V power going into LCD1 causing a brief flicker on LCD1.


  1. Is it expected that backlight of LCD (with I2C backpack) would leak current from VCC towards the SCL/SDA lines?
  2. How do I work around this?

I have seen mention of 33 ohm resistor on SCL/SDA bus (in-line), but I doubt that would help except to slow down the flicker leak.

I have partial drawings, but nothing fully drawn out to show the above situation. I am still bread-boarding it out.

Attaching a very basic drawing done with Falstad, hopefully it helps to illustrate the basics: diagram

  • \$\begingroup\$ Welcome to EE.SE :-) Please read the tour and help center to see how Stack Exchange sites work. You said: "I have partial drawings, but nothing fully drawn out to show the above situation" IMHO you need to supply an accurate schematic diagram (edit the question and add it there). I'm fairly sure that I know what type of problem you have (and it's a common one, especially for new engineers) but I can't tell you where & how to fix it as I can't refer to specific pins etc in your design. For future reference, see this checklist. \$\endgroup\$
    – SamGibson
    Commented Oct 6, 2018 at 14:18

2 Answers 2


You don't need level translation for I2C as it operates with pull-down only, you just need to set your pull up resistor to the 3.3V.

In general, unless otherwise specified by the datasheet, I2C pin cannot be higher than VCC, and if you power down your lcd, they will be. The reason is the embedded esd protection diode that will feed your lcd through the I2C line.

It's not easy to power down a device on a bus like this,you will need some specialized I2C chip for this porpose.

You rather check if the lcd has a sleep mode as most do.

  • \$\begingroup\$ Actually the common FET level translator solution can solve the power-down problem, but the power switching needs to be done with a high side switch not a low side one, and the switched supply connected to the respective side of the level translator. \$\endgroup\$ Commented Oct 6, 2018 at 18:03

It is non-conventional to power gate a component by switching it's GND line. Instead you should try switching the VCC line instead. It will be easier to manage current paths from signal lines into a component that may leak current to GND than the other way around.

  • \$\begingroup\$ Yes, but the I2C lines will also need to be switched, disabled, or held low. \$\endgroup\$ Commented Oct 6, 2018 at 18:04
  • \$\begingroup\$ @ChrisStrstton - The OP said they have a level translator to the LCD \$\endgroup\$ Commented Oct 7, 2018 at 21:41
  • \$\begingroup\$ There high side power gating can be configured to gate power also to the LCD side pull-up resistors and then disable the level translator. \$\endgroup\$ Commented Oct 7, 2018 at 21:44
  • \$\begingroup\$ Indeed, I said as much yesterday in a comment on the other answer. The point is it wasn't mentioned in your answer, and it's an easy oversight for someone like that asker trying this for the first time to make. \$\endgroup\$ Commented Oct 7, 2018 at 22:12

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