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I'm working on a circuit in Verilog to be implemented on a CPLD. The output of the circuit will drive a stepper motor. The input is a stream of pulses from a machine.

I generate a stepper pulse every X spindle pulses. No problem, works great.

While simulating, however, I noticed that if the stepper signal is high when the spindle pulses stop (say, someone turns off the machine), the stepper signal stays high. This is because I set it back to low on the leading edge of the spindle pulse, and there are no more.

This means that (with a poor implementation) the stepper could be run at full speed which would cause a machine crash. Now, I would hope the stepper controller would operate only on the leading edge, but you never know.

Finally, the question - since I can't depend upon my 'clock' (the spindle pulses) to continue ad infinitum, what's a good way to make the stepper pulse go low after 'a while.'

As you see, I can't even describe it properly so I can't Google it, lol. If someone could supply me with some words to search on (or better yet, describe a standard technique) I'll be off to the races.

Thanks!

EDIT -

I'm experimenting with the following (typed from memory...) Is this sadness, or a good idea?

always @(posedge Stepper) begin
     #50 // or whatever, this is a low Hz system...
     Stepper = 0;
     end

Or does the delay only work in the simulator?

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  • \$\begingroup\$ Regarding your edit, that delay only works for simulation. The only way to do this is by using another input or clock. If you use the input pulse as the clock, then when it stops there is nothing to drive the "set low after x ms" logic. I'll be doing some work in Xilinx ISE later - time permitting, if you need a hand with the code I can try and write a simple template to get you started. Just let me know the specs (e.g. stuff like the division ratio and timing) and I'll see what I can do. \$\endgroup\$ – Oli Glaser Sep 11 '12 at 16:22
  • \$\begingroup\$ I appreciate the offer, but I'll figure it out in short order. The journey is the destination, and all that. The CoolRunner includes clockage, I just have to use it. The only variable is how long the stepper pulse needs to be high - the rest is just pleasurable work. \$\endgroup\$ – Tony Ennis Sep 11 '12 at 16:45
  • \$\begingroup\$ Good stuff, I agree the knowledge certainly does stick better when you work through it yourself as much as possible. Anyway, if you run into problems and need any help, just update your question and post the code, or post it as an answer if you get it working. \$\endgroup\$ – Oli Glaser Sep 11 '12 at 17:06
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The best way (depending on how complex your final design will be) would probably be to use a separate fast CMOS oscillator for your CPLD system clock, and have it process the input pulses and output the stepper pulse.
This way, the clock is running all the time when the system is on, and it can time the period from the last input pulse - if it's above a certain limit, set the stepper line low.

This is the way a typical synchronous design works, you have an independent system wide clock and this is used to "read" (i.e. into a register) and process external asynchronous signals (as opposed to the external signals clocking the logic directly)

Another simpler way would be to have another input "reset" line that sets all the registers and outputs to a certain state when it goes low. You could then use a simple RC low pass filter on the input pulses so when they stop, the line drops low and the CPLD resets.

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