I'm working on a circuit in Verilog to be implemented on a CPLD. The output of the circuit will drive a stepper motor. The input is a stream of pulses from a machine.
I generate a stepper pulse every X spindle pulses. No problem, works great.
While simulating, however, I noticed that if the stepper signal is high when the spindle pulses stop (say, someone turns off the machine), the stepper signal stays high. This is because I set it back to low on the leading edge of the spindle pulse, and there are no more.
This means that (with a poor implementation) the stepper could be run at full speed which would cause a machine crash. Now, I would hope the stepper controller would operate only on the leading edge, but you never know.
Finally, the question - since I can't depend upon my 'clock' (the spindle pulses) to continue ad infinitum, what's a good way to make the stepper pulse go low after 'a while.'
As you see, I can't even describe it properly so I can't Google it, lol. If someone could supply me with some words to search on (or better yet, describe a standard technique) I'll be off to the races.
I'm experimenting with the following (typed from memory...) Is this sadness, or a good idea?
always @(posedge Stepper) begin #50 // or whatever, this is a low Hz system... Stepper = 0; end
Or does the delay only work in the simulator?