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When observing SPI communication with an oscilloscope, I see that there is some time between 'words' sent over the network. Red signal is SPI clk, and the blue is MISO.

enter image description here

My question is: What exactly happens in this time? As can be seen in my case this lasts about 500 ns. Is this duration dependent on the frequency of the SPI clock or on the CPU frequency?

I know that the number of bits that can be sent without this 'interruption' is dependent on the microcontroller. I have found microcontollers with 8 bit and 16 bit mode of operation. Are there also some with 32 bit mode of operation?

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It is very likely that this time is due to the micro-controller having to put the next byte in memory, either on a software or hardware level.

You can check the code and see if there is any bottleneck at this level, if for instance you send the data byte by byte with an interrupt.

Some micro-controllers have DMA buffer channels that can speed up transfer.

There are 8, 16 and 32bit micro-controller, depending on your application they can also speed up data transfer, although it is also related to the core frequency.

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Picture you provided does not make much sense. Communication involves another two wires - /SS and /MOSI, and you must consider them altogether. Picture shows that clock runs, then stops, then start again etc. and it is normal - clock is not required for idle devices.

My question is: What exactly happens in this time?

Clock is managed by the SPI master, thus if master does not provide clock then it either performs something for itself, or it is a part of protocol with SPI slave when master must wait. Impossible to elaborate without seeing the slave datasheet.

I know that the number of bits that can be sent without this 'interruption'

If you look at the clock is it not interrupting, it is suspending. You can judge on operation and action only in conjunction with /SS signal (and MOSI).

depending on your application they can also speed up data transfer, although it is also related to the core frequency.

Different SPI devices may have different protocol and data exchange techniques. Of course command send on MOSI can be considered as overhead, thus more data bits are sent within same transactions - the faster overall access will happen (a.k.a. block size).

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