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I want to ask the opposite of this question.
Here are the purpose of the bit scramblers:
Why do we need bit scrambling when using 8b/10b?
To refer to the original question, in SATA it is used to reduce the EMI emitted by the bus. If you look at the way 8b/10b encoding works, you'll see that it is entirely possible to have the same 10b word encoded throughout the message for certain 8b input values.
For example, the input 00100011 always encodes to 1001110001. So a message that consists entirely of 0x23 bytes will create a repeating sequence of:
1001110001100111000110011100011001110001...
This periodic sequence concentrates the signal energy into a small number of harmonics. Given the way EMC tests are conducted (looking at emissions within narrow bands) you are basically making life harder for yourself by allowing the overall energy to concentrate like this. By scrambling the data you statistically eliminate these sorts of periodic occurrences, and ensure that the signal energy is always spread out evenly across the available channel bandwidth.
I have found another aspect in the UG476 Xilinx's document.
DFE mode must be carefully considered in 8B/10B applications or where data scrambling is not employed. To properly adapt to data, the auto adaptation in DFE mode requires incoming data to be random. For example, in a XAUI application, the user payload data is non-scrambled and 8B/10B encoded. While the user payload is generally random, the frequency content of the data is inherently limited by the encoding, and there is nothing defined in the protocol to prevent repeated patterns from occurring. These repeated patterns can cause the auto adapting algorithms to drift away from the ideal equalization setting.
