How many LUTs are needed to implement a CPU? [closed]

I am looking to start my first FPGA based project, but as I am a complete beginner, I have very little idea how big an FPGA I need to implement my idea.

My project will be something similar to a CPU, so in order to get a sense of how big an FPGA I will need here is my question:

How many LUTs are typically required to implement a simple CPU? Is it hundreds, thousands, tens of thousands? I have seen a few open CPU cores online (e.g. The J1 and Opencores), but none of them seem to mention how many LUTs they might need.

All I need is a very rough idea of how many LUTs a CPU might need, or one or two examples to help me decide if this is worth further investigation.

The FPGA I have in mind is the Lattice Crosslink which contains 5936 LUTs. Would it be possible to implement any kind of CPU on that?

• Impossible to answer this - depends on the CPU, how good the compiler is, device etc. You could have a CPU that would "fit" in a small number of LUTs, but due to timing couldn't be realised in the FPGA. Commented Oct 11, 2018 at 9:52
• @awjlogan - So it's impossible to give any kind of guidance at all? Some kind of range, or one or two examples. Commented Oct 11, 2018 at 10:02
• @Rocketmagnet The current question is unanswerable, you'll need to make a few more design decisions beforehand, data widths, pipeline depths, supported commands are what I can think of off the top of my head. At a certain point a ballpark guess will be able to be made, but not right now. Commented Oct 11, 2018 at 10:15
• @Rocketmagnet the problem there then becomes "what do you call a CPU", I've seen companies implement 'CPUs' in a few 100 LUTs, but when you looked at the functionality, it was nothing more than a sequencer that read out the same N addresses from RAM and pushed the readback data to internal busses. Technically configurable with SW by overwriting the RAM, but not what I think of when I see CPU. Commented Oct 11, 2018 at 10:42
• I think people are being rather unhelpful in saying it's impossible to give ballpark numbers; in commercial FPGA and ASIC design there will generally be an area budget upfront before any Verilog is written, based on similar previous designs. Commented Oct 11, 2018 at 11:32

2 Answers

An example https://opencores.org/project/zipcpu :

The OpenRISC processor, however, is complex and hefty at about 4,500 LUTs. It has a lot of features of modern CPUs within it that ... well, let's just say it's not the little guy on the block. The Zip CPU is designed to be lighter weight, costing only about 2,300 LUTs with no peripherals, and 3,200 LUTs with some very basic peripherals.

Someone has build a small emulator for the 8-bit 6502 http://www.aholme.co.uk/6502/Main.htm:

This core manages performance equivalent to a 10 MHz 6502 using less than 700 LUTs in a Xilinx xc3s500e Spartan-3E FPGA.

That number seems very reasonable given that that 6502 only used about 3,000 transistors.

So the Lattice Crosslink should suit you with plenty of space for peripherals even for a 32-bit CPU, and is far larger than needed for an 8-bit simple CPU.

How long is a piece of string? It depends.

How many LUTs are typically required to implement a simple CPU?

How big is your CPU? How many features does it have? multiplier? divider? predictive branching? What frequency does it run at? What brand of FPGA? What family within a brand of FPGA? Even which version of the toolset for that FPGA.

All these factors affect how much logic the CPU will require, and how much memory and logic resource it will require.

Is 5963 LUTs a lot?

Maybe, maybe not. Again it depends on your design. For a massive complete system it is tiny. For a little CPU and a few peripherals it could be more than enough.

Now that's out of the way, a better question would be how do I go about checking?

1. To start off, pick a vendor - Altera/Intel? Xilinx? Lattice? etc. Up to you.

• Pick one that you like the toolset (development environment)
• One for which your desired electronics supplier has good stock.
• Compare also prices - you probably want to go with an entry level series unless you have need to features like DSP and Gbps transceivers.
• Pick one that you have or can get the tools to program.

To be honest it doesn't really matter which you pick, but you need to pick one.

2. Download and install the toolset for that vendor. These a \$%£& huge packages, so you only really want to be installing one, hence picking an FPGA family first.

3. Once you have the toolset installed, create a project. Many allow you to create projects that target a specific series of FPGA as opposed to any specific device. If not, simply select the largest device in the family that you have chosen - it doesn't matter if you don't go on to use that device at this point.

4. Design your CPU in your chosen HDL (*Verilog, VHDL, etc.). You can download IP cores for the internet (though be wary, many are not verified and in many cases more hassle than they are worth), or try out the vendor specific IP that comes with the toolset (some may require pricey licenses).

5. Test compile - this is the key point. This is the point at which your question is answered. The FPGA toolset will tell you how many resources are required for your design. At this point you can then change your target FPGA to a smaller and cheaper part in the selected family and recompile to check that it still fits.

At this point you are ready to start tailoring your design to the chosen FPGA. You can start looking at pin-outs and hardware resources (DSP, RAM, etc.). Make pin assignments and compile an actual design - this can be where the tools bite back, it's very easy to select a pin that cannot physically be used in the way you want (e.g. feeding clock into non-dedicated pin, using programming pin for IO, we've all done it).

Only once you have a synthesisable test design do you even thing about designing hardware or ordering parts.

• Can you give any kind of guidance at all? Some kind of range, or one or two examples. Commented Oct 11, 2018 at 10:13
• @Rocketmagnet I've literally just explained how to find out - test compile for an FPGA - does that not count as guidance... There are far too many variables. A LUT itself is not even a unit of measurement - different FPGAs have different sized lookup tables with different features. Especially when you start having RAM involved. Commented Oct 11, 2018 at 10:25
• @Rocketmagnet you're new to FPGAs by your own admission. I'm explaining to you that your question is backwards. You don't start by deciding how many LUTs you need, you start by designing your system. You then choose an FPGA that fits. Commented Oct 11, 2018 at 10:29
• Have you ever seen a CPU implemented with less than 6000 LUTs ? Commented Oct 11, 2018 at 10:36