Based on my understanding of VHDL, a port map statement looks like:

signal reset_n : std_logic;
...

port map (
    ...
    reset_n => reset_n
);

... where the LHS of the port map assignment is the port name on your component and the RHS is a signal you've declared above.

But for a generic map, what does the RHS refer to?

...
generic map (
    ...
    baud_rate => baud_rate
);

The LHS is the generic field in the entity to be written to by whatever the RHS specifies (right?), the VHDL way of passing a value into your generic. But if the RHS is not declared as a signal (which it is not, based on test benches I've looked at), what is being assigned/wired to the LHS? What is going on under the hood?

closed as off-topic by Dave Tweed Oct 11 at 17:32

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  • RHS is the value to be assigned to the LHS. As simple as that. If it is not defined in your design, then it has a bug. hdlworks.com/hdl_corner/vhdl_ref/VHDLContents/GenericMap.htm – Eugene Sh. Oct 11 at 16:03
  • Where would that value be assigned? If you simply have baud_rate => baud_rate in your generic map, is the RHS the value assigned in the generic(...) in your component above? – schadjo Oct 11 at 16:05
  • 1
    The baud_rate on the left is not the same baud_rate on the right. LHS is the generic name, RHS is the expression to be assigned, and in your case baud_rate has to be defined somewhere outside the generic block – Eugene Sh. Oct 11 at 16:08
  • -1 You posted the same question on two forums near simultaneous. That is against the rules , impolite and very much frowned upon. – Oldfart Oct 11 at 17:16
  • It's a stupid rule. – schadjo Oct 11 at 17:17