Based on my understanding of VHDL, a port map statement looks like:
signal reset_n : std_logic; ... port map ( ... reset_n => reset_n );
... where the LHS of the port map assignment is the port name on your component and the RHS is a signal you've declared above.
But for a generic map, what does the RHS refer to?
... generic map ( ... baud_rate => baud_rate );
The LHS is the generic field in the entity to be written to by whatever the RHS specifies (right?), the VHDL way of passing a value into your generic. But if the RHS is not declared as a signal (which it is not, based on test benches I've looked at), what is being assigned/wired to the LHS? What is going on under the hood?