Not exactly, no. In a microcoded processor, what happens is that the ISA is read by the processor and each instruction (and, potentially, some part of the current state of the processor, e.g. flags) is used as an index into a lookup table that determines what exactly the processor does. Each instruction is allowed to have multiple entries in that table that are then performed sequentially. No direct translation from the primary ISA to a "hardware language" is ever produced -- it's more a case of an extra level of indirection between the ISA and the hardware is used, with the contents of the microcode usually just being a bunch of signals that directly control the hardware of the processor (e.g. selecting the inputs to multiplexers, controlling when registers are written to, etc).
The real difference between this and a hardwired processor is that the microcode is written as a lookup table rather than the controls being generated by fixed logic. Of course, as we all know the two are actually logically equivalent, so in reality there's not much actual difference between the two.
Where a hardwired processor really differentiates itself from a microcoded one is that it is much easier to implement pipelining for a hardwired design, so most pipelined designs avoid using microcode as much as possible. This is made easier if the ISA doesn't specify many operations that need to be performed sequentially, which is where RISC comes in -- RISC instructions are generally different from CISC ones because they only do one thing, i.e. either access memory or perform calculations, whereas CISC architectures often do both in the same instruction. This makes designing a fixed pipeline for a RISC architecture much easier.