I am following an Altera online course on their timing analyzer software called TimeQuest. In it, their recommend that, at the very least, all clock and I/O ports be constrained.

In my FPGA design, I am generating an output clock pin to an ADC by muxing various clocks (some generated internally). As far as I know, the way to constrain output ports is to use the SDC command set_output_delay, by specifying setup and hold constraints with respect to a clock.

In my case, there does not seem to be any meaningful clock to base the set_output_delay contraint upon. How should my output clock be constrained? Does it even make sense to try to constrain this specific output port?


Well, it does make sense to apply meaningful constraints if you actually care about timing and it does matter. How to constrain it heavily depends on your design. Thankfully, Altera has tons of examples for different cases.

But if you don't care at all then the best way to go is to mark that path as a false path so that Time Quest is happy and synthesizer does not hang for hours trying to route your design in order to meet timing requirements that you don't really have. That you can do with set_false_path command. For example:

set_false_path -from * -to [get_ports { output_port }]

(where output_port is a module's top level port assigned to a pin)

If Time Quest gives you a diagnostics that not every output port has a delay, you may want to add some dummy delay as well, like this:

set_output_delay -clock [get_clocks src_clk] 2 [get_ports { output_port }]

For a more practical example, you can check out this SDC file for this top-level module, the path to led_n is market as false path there since I pretty much don't care about timing from my logic to the LEDs.

Hope it helps.

  • \$\begingroup\$ In this dummy delay, what clock do you specify if there are multiple source clocks? Also, how did you choose the number 2? \$\endgroup\$
    – Randomblue
    Sep 11 '12 at 21:06
  • \$\begingroup\$ @Randomblue: I have specified a clock input to the FPGA (in_clk_100), which is a root of all the clocks in that design. It doesn't really matter what clock you specify since all possible paths are market as false (-from *). Same thing about 2 - it doesn't matter, make it 3 if you like it better, as long as it is not 0 - time quest will be happy. \$\endgroup\$
    – user8459
    Sep 11 '12 at 21:21

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