I am following an Altera online course on their timing analyzer software called TimeQuest. In it, their recommend that, at the very least, all clock and I/O ports be constrained.
In my FPGA design, I am generating an output clock pin to an ADC by muxing various clocks (some generated internally). As far as I know, the way to constrain output ports is to use the SDC command
set_output_delay, by specifying setup and hold constraints with respect to a clock.
In my case, there does not seem to be any meaningful clock to base the
set_output_delay contraint upon. How should my output clock be constrained? Does it even make sense to try to constrain this specific output port?