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By looking at some of the details of the Altera timing analyzer TimeQuest, the concept of a "combinatorial feedback loop" was mentioned. The obvious search is not terribly helpful and there doesn't seem to be a Wikipedia article on the topic.

What exactly is a combinatorial feedback loop in the context of FPGA and ASIC design? Is there a typical example to illustrate the concept?

If an example is provided using an HDL, I much prefer Verilog over HDL.

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A combinatorial feedback loop is created when the output of either a gate or a combinatorial path is fed back as an input to the same gate or to another gate earlier in the combinatorial path. The most simple case may look like this:

always @ (a or b)
  a = a + b;
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A combinatorial loop is when a loop is formed where the output of a gate feeds back to the input without passing through any sequential element. The simplest example would be an inverter with the output tied to the input. Combinatorial loops are almost always errors, but sometimes they show up in ASIC designs in the form of long chains of inverters connected in a loop. These can be used to provide information about the speed of the device technology.

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  • \$\begingroup\$ When using PLD/CPLD or hardwired-logic designs, combinatorial feedback loops are often a useful way to generate asynchronous latches. They can be dangerous in FPGAs, though, because correct operation generally requires that the outputs of certain gates not change before their inputs. Such a guarantee would always be met by physical gates, and would usually be met in a CPLD, but will often not be met in an FPGA, where it's entirely possible for an input stimulus to affect the "output" of a gate before it affects the input. \$\endgroup\$ – supercat Sep 19 '12 at 20:18
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An incompletely specified case statement can cause this. In the undefined cases, the output isn't changed. And the output is based on the previous output, so there is a loop. This also creates latch.

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  • \$\begingroup\$ I have a strong feeling that FPGA synthesis tools implement inferred latches using D-type flops and do not create combinatorial loops. At least for Altera. No? \$\endgroup\$ – user8459 Sep 11 '12 at 21:23
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    \$\begingroup\$ No, but that's beside the point anyway. It's the logical combinatorial loop that creates the latch in the first place, not the other way around. \$\endgroup\$ – Dave Tweed Sep 11 '12 at 22:07
  • \$\begingroup\$ @VladLazarenko: A clocked register (D flip flop) which doesn't have async set/reset signals cannot behave like combinatorial logic, nor can combinatorial logic behave like a clocked register unless gates have a guaranteed minimum propagation time. \$\endgroup\$ – supercat Sep 19 '12 at 20:41

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