By looking at some of the details of the Altera timing analyzer TimeQuest, the concept of a "combinatorial feedback loop" was mentioned. The obvious search is not terribly helpful and there doesn't seem to be a Wikipedia article on the topic.
What exactly is a combinatorial feedback loop in the context of FPGA and ASIC design? Is there a typical example to illustrate the concept?
If an example is provided using an HDL, I much prefer Verilog over HDL.