A similar question is asked here: "two bypass/decoupling capacitors" rule? But that question was about parallel bypass capacitors without mentioning package size (but the answers mostly assumed paralleling parts with different package sizes), while this one is specifically about parallel bypass capacitors in the same package size.

I recently attended a course on High speed digital design, where the lecturer went to some length to explain that a capacitor's performance for decoupling was limited almost entirely by its inductance, which in turn was almost entirely due to its size and placement.

His explanation seems to clash with the advice given in many datasheets, which suggest multiple values of decoupling capacitor even though they have the same package size.

I believe his recommendation would be: for each package size, choose the highest capacitance that's feasible, and place it as close as possible, with smaller packages closest.

For example, in a schematic from Lattice Semiconductor, they suggest the following:

  • 470pF 0201
  • 10nF 0201
  • 1uf 0306

Multiple decoupling capacitors

Q1: Is that 470pF capacitor really helping?

Q2: Wouldn't it make sense to replace all three of them with a single 1uF capacitor in an 0201 package?

Q3: When people say that a higher value capacitor is less useful at higher frequencies, how much of that is due to the capacitance, and how much is due to the increased package size usually associated with larger caps?

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    \$\begingroup\$ No, people do it all just for fun and to pay more money on their BOM. \$\endgroup\$ – PlasmaHH Oct 12 '18 at 9:49
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    \$\begingroup\$ @PlasmaHH Honestly there's so much misinformation about decoupling swirling around that your sarcastic statement is actually quite accurate. More accurately, caps are cheap and their cost is irrelevant in all but the highest volume products, so people will just take a shotgun approach that's "safe." Ironically, sometimes they shoot themselves in the foot when using an array of values as it can easily cause anti-resonance spikes in their impedance that amplify noise. \$\endgroup\$ – jalalipop Oct 12 '18 at 11:58
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    \$\begingroup\$ I also disagree wholly with the decision to mark this as duplicate. The linked question wasn't asking about caps in the same package. Rocketmagnet has a point and if you've ever done a PI/decoupling analysis of a board you'll usually come to the same conclusion. \$\endgroup\$ – jalalipop Oct 12 '18 at 12:00
  • \$\begingroup\$ @jalalipop - Thanks for the support, please could you vote to re-open this question? \$\endgroup\$ – Rocketmagnet Oct 12 '18 at 15:33
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    \$\begingroup\$ There is also the issue of big MLCC capacitors in small packages using different dielectrics which lose capacitance when biased (and they will always be biased when decoupling). electronics.stackexchange.com/questions/103785/… This is sometimes extreme (-80% at rated voltage) and means that you may be better off with a few 1uF 0805 caps than one 10uF in the same package. \$\endgroup\$ – jpc Oct 12 '18 at 21:58

This is a question I've been wondering my self from time to time, and I haven't found an answer yet. I did a simulation with LTSpice to get some kind of answer. I chose a couple of capacitors from Murata pretty much on random: 4.7 µF https://psearch.en.murata.com/capacitor/product/GRM155R61A475MEAA%23.html and 100nF https://psearch.en.murata.com/capacitor/product/GRM152B31A104KE19%23.html

I set the ESL for both caps to 300p and ESR for 100 nF to 30m and for 4.7 µF to 8m. With these values their impedance seems to match quite well to that in the Murata's graphs. (To be precise the ESL is not exactly the same, but it is close enough so I'll use the same value)

I simulated with only 4.7 µF, 4.7 µF + 100 nF and 2 x 4.7µF. I added 1 nH inductance between the capacitors, to simulate the trace connecting them.

enter image description here

The results are interesting, but not very unexcepected enter image description here Adding the 100 nF increases filtering, except for the antiresonance frequency. Adding another 4.7 µF has the same effect, except that there is no antiresonance. The 100 nF works better at its self resonant frequency, but it's effect is smaller than the lost filtering performance of the antiresonance. Based on this, I'd just add more bigger capacitors.

But, if you e.g. had a noise problem at 30 MHz, then it makes sense adding that 100 nF capacitor, because it does filter that frequency well.

Q1: Is that 470pF capacitor really helping?

At it's resonant frequency it is. If there is no noise at that frequency, then not that much.

Q2: Wouldn't it make sense to replace all three of them with a single 1uF capacitor in an 0201 package?

Would be probably better to add two 1 µF 0201 capacitors. Then if you do run in to trouble at some certain frequency, you could change one of them to capacitor that has SRF at that frequency. You could also leave the other one as not assembled, but capacitors are cheap so why bother.

Q3: When people say that a higher value capacitor is less useful at higher frequencies, how much of that is due to the capacitance, and how much is due to the increased package size usually associated with larger caps?

Pretty much is about the package size. Of course the higher SRF helps again, but only if you have noise at that frequency. Otherwise it is just better to double the biggest capacitance.

  • \$\begingroup\$ Thanks for this, it's very interesting. I think what I'll do is, next time I make a board with some high speed components, I'll try both the manufacturers recommended decoupling, and my own version of decoupling, and scope both boards. Then I'll post the results here as an answer. \$\endgroup\$ – Rocketmagnet Dec 28 '18 at 22:02
  • \$\begingroup\$ I'm looking forward to seeing the results. Do the tests so that you have an equal amount of capacitors in both versions. I think that my simulation is correct on that "more capacitors is better", but the interesting question is "is more capacitor values better" \$\endgroup\$ – TemeV Dec 29 '18 at 8:00

The answer is simple:

  • There aren't 10nF NP0 dielectric capacitors in size 0201.

The maximum capacity for these is about 1nF. So either you need a bigger package or you have to stick to the X7R dielectric, which behaves not so well at >10MHz.


Read the duplicate answer for all the theory, but here's a good rule of thumb:

The larger value capacitors are less effective at higher frequencies and of course the smaller value capacitors won't be effective at a lower frequency.

The different capacitors therefore each provide stabilization for a different frequency band. Depending on your application and the amount of 'noise' it generates at different frequencies, you need to apply capacitors with specific values to stabilize the power bus.

A general rule is at least 1-10uF plus a 100nF, but the above example looks quite fine for a circuit with a high clock speed. For audio applications you want something similar, but with much higher value for supporting the demands on the power bus with music frequencies.

Q1: Yes, it kills high frequency oscillation and noise. Q2: No, you may have a problem with high frequency noise.

PS: The small capacitors should be placed closest to the IC pins to minimize the inductance between the capacitor pins and the IC pins. The larger value capacitors can be placed further away if necessary.

  • \$\begingroup\$ I saw the other question, but I didn't think it quite addressed my question, (unless I'm confused). \$\endgroup\$ – Rocketmagnet Oct 12 '18 at 10:35
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    \$\begingroup\$ What I'm trying to get at is: when people say that a higher value capacitor is less useful at higher frequencies, how much of that is due to the capacitance, and how much is due to the increased package size usually associated with larger caps? \$\endgroup\$ – Rocketmagnet Oct 12 '18 at 10:38
  • \$\begingroup\$ this is what matters: Real capacitors have inductance and resistance. The objective of a bypass capacitor is to rapidly respond to current transients in order to maintain a stable voltage. The series inductance and resistance are counter to that goal. \$\endgroup\$ – mike65535 Oct 12 '18 at 11:18
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    \$\begingroup\$ None of this answers his question. \$\endgroup\$ – jalalipop Oct 12 '18 at 11:58
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    \$\begingroup\$ @mike65535 - Thanks for that. However, as I mentioned in my question, I've just been on a course on high speed digital design. It would be fairly surprising if I didn't know that capacitors had inductance. In fact, I think I mentioned inductance in my question. Please can you carefully read my question before assuming I'm a newbie, and just offering the default answer about decoupling capacitors. \$\endgroup\$ – Rocketmagnet Oct 12 '18 at 13:26

Putting two different types of capacitors in parallel, like an electrolytic and a ceramic, will provide a low impedance over a much wider frequency range.

Electrolytics have significant inductance. Their impedance at high frequencies will often not be enough to bypass a chip. A ceramic capacitor in the range of 0.01 to 0.1uF or so will have a low impedance into the tens of megahertz, typically.

I use op amps in linear circuits. Op amps will oscillate and/or exhibit very poor transient response if not properly bypassed. I solder a 0.1 uF/50V ceramic capacitor directly to the power supply leads of the chip, on the bottom of the board. The electrolytic capacitor is chosen according to the load requirements placed on the chip; 1 to 100 uF is common. The electrolytic should be as close as possible to the chip, but 20-30 mm is usually acceptable if necessary.

  • \$\begingroup\$ This question is specific to ceramic bypass capacitors and their package sizes. It should be clear that it has nothing to do with the different capacitor types. \$\endgroup\$ – Edgar Brown Dec 22 '18 at 23:26

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