I have a small test design in an Altera CycloneIV GX, where I'd like to output data synchronous to a gated clock.

AN433 gives a lot of examples, but they all define output path constraints relative to an internal clock.

This seems to introduce tighter constraints than necessary, as I don't care about internal delays as long as the end result is consistent.

Is there a way to define setup and hold time requirements for an I/O buffer's output relative to another I/O buffer's output?

  • \$\begingroup\$ It sounds like you're looking for a skew constraint. That exists in some FPGA families, but not all. The part has to be characterised for it, the tools have to use it correctly, so it's not something that can be bolted-on as an afterthought. Look carefully through the documentation for your particular part and tools. If you can't find it, you can't constrain it, but you may be able to create proxies for it which you can constrain, albeit not as accurately. \$\endgroup\$ – Neil_UK Oct 12 '18 at 10:35

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